Apparatus and method for gallium nitride (GaN) amplifiers

1. An electronic circuit for providing a bias voltage to an output Gallium Nitride (GaN) field effect transistor (FET) comprising:

a first reference GaN FET having a gate, a source and a drain electrode;

a positive voltage supply connected to the drain electrode of said first reference GaN FET;

a first resistor device having a first terminal end coupled to the drain electrode of the first reference GaN FET, and a second terminal end coupled to the positive voltage supply;

a negative voltage supply coupled to said source electrode of said first reference GaN FET via a second reference GaN FET; and

an output node terminal coupled to the first terminal end of the first resistor and the drain electrode of said first reference GaN FET for providing the bias voltage to said output GaN FET,

wherein said gate electrode of said first reference GaN FET is coupled to said negative voltage supply via a third resistor, and said source electrode of said first reference GaN FET is coupled to said negative voltage supply via said second reference GaN FET, thereby producing a voltage level at said gate electrode that is less than a voltage level at said source electrode.

2. The circuit of claim 1 , wherein said second reference GaN FET exhibits a resistance to produce a target bias voltage at said output node terminal.

3. The circuit of claim 2 , wherein the resistance exhibited by said second reference FET varies with temperature.

4. The circuit of claim 3 , wherein said second reference GaN FET has its gate electrode coupled to its drain electrode via a second resistor.

5. A reference bias circuit for providing a desired gate bias voltage to an output wide band gap field effect transistor (FET) comprising:

a first reference FET having a gate electrode, a drain electrode coupled to a positive voltage supply, and a source electrode coupled to a negative voltage supply;

a first resistor coupled between said drain electrode of said first reference FET and said positive voltage supply;

a second reference FET coupled between said source electrode of said first reference FET and said negative voltage supply;

an electrical node connecting said first resistor and said drain electrode of said first reference FET, and coupled to a gate electrode of said output wide band gap FET to provide a reference bias voltage thereto; and

a plurality of diode-connected FETs connected in series between said positive voltage supply and said gate electrode of said first reference FET, said plurality of diode-connected FETs configured to produce a temperature dependent bias voltage at said gate electrode of said first reference FET, to thereby modulate a current between said drain electrode and said source electrode of said first reference FET based on temperature.

6. The reference bias circuit of claim 5 , wherein each of said plurality of diode-connected FETs comprises Gallium Nitride (GaN).

7. The reference bias circuit of claim 5 further comprising:

a level shifting resistor coupled between said electrical node and said negative voltage supply, wherein a conductive path is defined from said positive voltage supply through said first resistor, said electrical node and said level shifting resistor to said negative voltage supply.

8. The reference bias circuit of claim 5 , further comprising:

an enable circuit comprising:

an enable FET having a gate electrode coupled to said negative voltage supply and to said gate electrode of said output wide band gap FET, a drain electrode coupled to said source electrode of said first reference FET, and a source electrode coupled to an enable pin; and

a pair of series connected resistors connected between said gate electrode of said enable FET and said enable pin, wherein said source electrode of said enable FET is coupled to said enable pin at a node between a first resistor and a second resistor of said pair of series connected resistors.

9. The reference bias circuit of claim 8 , wherein said enable FET comprises Gallium Nitride (GaN).

10. The reference bias circuit of claim 5 , further comprising:

a capacitor coupled between said gate electrode of said output wide band gap FET and a reference potential, wherein said capacitor is configured to filter out radio frequency (RF) signals applied at said gate of said output wide band gap FET and prevent said RF signals from reaching said electrical node coupled to said first reference FET.

11. The reference bias circuit of claim 5 , wherein said output wide band gap FET comprises Gallium Nitride (GaN).

12. The reference bias circuit of claim 5 , wherein said first reference FET comprises Gallium Nitride (GaN).

13. The reference bias circuit of claim 5 , wherein said second reference FET comprises Gallium Nitride (GaN).

14. A circuit for providing bias to an output Gallium Nitride (GaN) field effect transistor (FET) comprising:

a radio frequency (RF) input signal applied to a gate electrode of the output GaN FET;

a positive voltage source connected to a drain electrode of the output GaN FET;

a reference voltage connected to a source electrode of the output GaN FET;

a reference FET between the source electrode of the output GaN FET and the reference voltage, the reference FET having a drain electrode connected to the source electrode of the output GaN FET, a gate electrode connected to the source electrode of the output GaN FET via a resistor, and a source electrode connected to the reference voltage; and

a negative voltage source connected to the gate electrode of the output GaN FET via a filtering resistor and a filtering inductor.

15. The circuit of claim 14 , further comprising:

an RF output generated between the positive voltage source and the drain electrode of the output GaN FET.

16. The circuit of claim 15 further comprising a filtering inductor between the positive voltage source and the RF output.

17. The circuit of claim 16 , further comprising:

a filtering capacitor between the node producing the RF output and a terminal providing an output signal of the output GaN FET.