Semiconductor package with Pillar-Top-Interconnection (PTI) configuration and its MIS fabricating method
Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.
1. A semiconductor package comprising:
a first redistribution layer, the first redistribution layer including a plurality of first fan-in pads and a plurality of first fan-out pads;
a plurality of first metal pillars disposed on the first fan-out pads;
a first chip bonded onto the first redistribution layer and electrically connected to the first fan-in pads;
a first molding core formed to encapsulate the first redistribution layer and the first chip, the first molding core having a first bottom surface coplanar to a surface of the first redistribution layer and a first top surface, wherein the first top surface is a planar surface having first dimple holes, each of the first dimple holes configured to expose a first pillar top portion of one of the first metal pillars;
a second redistribution layer disposed on the first top surface of the first molding core, the second redistribution layer including a plurality of second fan-in pads and a plurality of second fan-out pads, wherein the second fan-out pads are formed in the first dimple holes and configured to electrically couple to the first pillar top portions of the first metal pillars;
a plurality of second metal pillars disposed on the second fan-out pads;
a second chip bonded onto the second redistribution layer and electrically connected to the second fan-in pads; and
a second molding core formed on the first top surface of the first molding core and configured to encapsulate the second redistribution layer and the second chip, the second molding core having a second top surface, wherein the second top surface is a planar surface having second dimple holes, each of the second dimple holes configured to expose a second pillar top portion of one of the second metal pillars,
wherein the second fan-out pads are inverted cone pads embracing the first pillar top portions and pillar sidewalls of the first metal pillars.
2. The semiconductor package as claimed in claim 1 , wherein the first dimple holes do not penetrate through the first molding core.
3. The semiconductor package as claimed in claim 2 , wherein a depth of the first dimple holes is greater than an encapsulating thickness of the first molding core over the first chip.
4. The semiconductor package as claimed in claim 1 , wherein a first pillar height of the first metal pillars is smaller than a first package thickness of the first molding core between the first bottom surface and the first top surface but not less than a first chip-bonding height of the first chip.
5. The semiconductor package as claimed in claim 1 , wherein the first chip is flip-chip bonded to the first fan-in pads by a plurality of first bumps of the first chip.
6. The semiconductor package as claimed in claim 1 , further comprising a plurality of solder balls jointed to the first fan-out pads and extruded from the first bottom surface.