ESD clamp circuit
View Patent ↗An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor, and a first resistor connected in series with the capacitor between the power and ground supplies. The ESD clamp circuit also includes a clamp transistor having a first terminal connected to the power supply and a second terminal connected to the ground terminal, an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to the gate of the clamp transistor, a feedback transistor connected across the inverter, and a second resistor having a first terminal connected to the gate of the clamp transistor and to a second terminal to the ground supply.
1. An electrostatic discharge (ESD) clamp circuit comprising:
a power supply;
a ground supply;
an ESD detection transistor;
a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor;
a first resistor being a polysilicon resistor and having a first terminal connected to the gate of the ESD detection transistor and a second terminal connected to the ground supply;
a clamp transistor comprising a multi-finger structure having a first terminal connected to the power supply and a second terminal connected to the ground supply and configured to shunt a current associated with an ESD pulse;
an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to a gate of the clamp transistor;
a feedback transistor having a gate connected to the gate of the clamp transistor, a first terminal connected to the power supply and a second terminal connected to the first terminal of the ESD detection transistor; and
a second resistor having a first terminal connected to the gate of the clamp transistor and a second terminal connected to the ground supply,
wherein the capacitor and the first resistor together form an RC circuit having a time constant smaller than a rise time of the power supply and greater than a width of the ESD pulse.
2. The ESD clamp circuit of claim 1 , wherein the ESD detection transistor is an n-channel transistor.
3. The ESD clamp circuit of claim 1 , wherein the capacitor is a parasitic capacitance of an n-channel transistor or a parasitic capacitance of a p-channel transistor.
4. The ESD clamp circuit of claim 1 , wherein the capacitor is a parasitic capacitance of a metal oxide semiconductor (MOS) varactor or a parasitic capacitance of a diode.
5. The ESD clamp circuit of claim 1 , wherein the feedback transistor is a p-channel transistor having the gate connected to the output of the inverter, the second terminal connected to the input of the inverter, the first terminal and a substrate connected to the power supply.
6. The ESD clamp circuit of claim 1 , wherein the inverter is a single stage inverter configured to reduce a trigger time of the ESD clamp circuit and increase a turn-on speed of the clamp transistor.
7. The ESD clamp circuit of claim 1 , wherein the second resistor is a polysilicon resistor, an NMOS transistor having a gate connected to the power supply, a PMOS transistor having a gate connected to the ground supply, or a parasitic metal resistor.
8. An electrostatic discharge (ESD) clamp circuit, comprising:
a power supply;
a ground supply;
an ESD detection transistor;
a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor;
a first resistor having a first terminal connected to the gate of the ESD detection transistor and a second terminal connected to the ground supply;
a clamp transistor comprising a plurality of n-channel transistors connected in parallel, each of the n-channel transistors having a drain terminal connected to the power supply and a source terminal connected to the ground supply and configured to shunt a current associated with an ESD pulse;
an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to a gate of the clamp transistor;
a feedback transistor having a gate connected to the gate of the clamp transistor, a first terminal connected to the power supply and a second terminal connected to the first terminal of the ESD detection transistor; and
a second resistor having a first terminal connected to the gate of the clamp transistor and a second terminal connected to the ground supply,
wherein the capacitor and the first resistor together form an RC circuit having a time constant smaller than a rise time of the power supply and greater than a width of the ESD pulse.
9. The ESD clamp circuit of claim 8 , wherein the capacitor is a parasitic capacitance of an n-channel transistor.
10. The ESD clamp circuit of claim 8 , wherein the capacitor is a parasitic capacitance of an MOS varactor.
11. The ESD clamp circuit of claim 8 , wherein the capacitor is a parasitic capacitance of a diode.
12. The ESD clamp circuit of claim 8 , wherein the plurality of n-channel transistors each comprise a parasitic capacitance between a gate oxide layer and the drain terminal, a sum of the parasitic capacitances forming with the second resistor a gate-coupled circuit configured to uniformly turn on the clamp transistor during an ESD event.
13. The ESD clamp circuit of claim 12 , wherein the second resistor is configured to discharge excess energy stored in the gate oxide layer.
14. The ESD clamp circuit of claim 8 , wherein the first resistor is a parasitic metal resistor.