Active drain terminated distributed amplifier
A distributed amplifier is disclosed having a plurality of amplifier sections, each having an input gate and an output drain, and a first plurality of inductive elements coupled in series between a DA input terminal and a gate termination terminal to form a first plurality of connection nodes. Each of the connection nodes is coupled to a corresponding adjacent pair of the first plurality of inductive elements and to a corresponding input gate of the plurality of amplifier sections. A second plurality of inductive elements is coupled in series between a drain termination terminal and a DA output terminal to form a second plurality of connection nodes, each being coupled to a corresponding adjacent pair of the second plurality of inductive elements and to a corresponding output drain of the plurality of amplifier sections. An active impedance termination circuitry has a termination output coupled to the drain termination terminal.
1. A distributed amplifier (DA) comprising:
a plurality of amplifier sections that each has an input gate and an output drain;
a first plurality of inductive elements coupled in series between a DA input terminal and a gate termination terminal to form a first plurality of connection nodes, each being coupled to a corresponding adjacent pair of the first plurality of inductive elements and to a corresponding input gate of the plurality of amplifier sections;
a second plurality of inductive elements coupled in series between a drain termination terminal and a DA output terminal to form a second plurality of connection nodes, each being coupled to a corresponding adjacent pair of the second plurality of inductive elements and to a corresponding output drain of the plurality of amplifier sections; and
active impedance termination circuitry having a termination output coupled to the drain termination terminal and a termination input that is coupled to a reference node, wherein the active impedance termination circuitry includes a first one of the plurality of amplifier sections configured as a common source amplifier and remaining ones of the plurality of amplifier sections configured as cascode amplifiers.
2. The DA of claim 1 wherein the reference node is at lower potential than the drain termination terminal during operation.
3. The DA of claim 1 wherein the reference node is one of the first plurality of connection nodes closest to the DA input terminal.
4. The DA of claim 1 wherein the active impedance termination circuitry does not include a termination resistor.
5. The DA of claim 1 wherein the first one of the plurality of amplifier sections is a field effect transistor (FET) configured as a common source amplifier having increased drain to gate spacing relative to a drain to gate spacing of remaining ones of the plurality of amplifier sections.
6. The DA of claim 1 wherein the first one of the plurality of amplifier sections is a FET configured as a common source amplifier with a source resistor having a resistance value that determines drain terminal impedance at the drain termination terminal.
7. The DA of claim 1 wherein the first one of the plurality of amplifier sections is a FET configured as a common source amplifier with a gate bias resistor that has a resistance greater than 10,000 Ohms.
8. The DA of claim 1 wherein the first one of the plurality of amplifier sections is a FET configured as a common source amplifier with a gate bias resistor that has a resistance greater than 1,000 Ohms.
9. The DA of claim 1 wherein the first one of the plurality of amplifier sections is a FET configured as a common source amplifier with a gate bias resistor that has a resistance greater than 500 Ohms.
10. The DA of claim 1 wherein the first one of the plurality of amplifier sections is a FET configured as a common source amplifier with a gate resistor and a gate capacitor coupled in parallel between a gate of the FET and the reference node.
11. The DA of claim 1 wherein the first one of the plurality of amplifier sections comprises a first FET and a second FET configured as a cascode amplifier such that the first FET has a gate input coupled to the reference node and the second FET has a drain output coupled to the drain termination terminal.
12. The DA of claim 11 wherein the second FET has a gate coupled to the drain termination terminal through a feedback resistor and a feedback capacitor that are coupled in series.
13. The DA of claim 12 wherein the feedback resistor is a resistive FET.
14. The DA of claim 11 wherein a gate of the second FET is coupled to ground through a gate resistor and a gate capacitor coupled in series.
15. The DA of claim 11 wherein a gate of the second FET is coupled to ground through a gate capacitor.
16. The DA of claim 1 further including an active gate termination coupled to the gate termination terminal.
17. The DA of claim 1 wherein signal gain between the DA input terminal and the DA output terminal remains within 1 dB of an ideal flat response over a bandwidth that ranges between 0 Hz and 50 GHz during operation.
18. The DA of claim 1 wherein signal gain between the DA input terminal and the DA output terminal remains within 1 dB of an ideal flat response over a bandwidth that ranges between 0 Hz and 100 GHz during operation.
19. The DA of claim 1 wherein the active impedance termination circuitry is a non-amplifying load during operation.
20. The DA of claim 1 wherein a bias voltage for the active impedance termination circuitry is no greater than an output voltage at the DA output terminal during operation.
21. The DA of claim 1 wherein a bias voltage for the active impedance termination circuitry is no greater than a drain voltage of any one of the plurality of amplifier sections during operation.