Gap fill self planarization on post EPI
The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.
1. An integrated chip, comprising:
an epitaxial source/drain region protruding outward from within a substrate to a location over the substrate;
a first gate structure separated from the epitaxial source/drain region by a first gap, wherein the first gate structure comprises a conductive gate electrode;
a flowable dielectric material disposed within the first gap;
a pre-metal dielectric (PMD) layer arranged above the flowable dielectric material, wherein the PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode; and
a metal contact electrically coupled to the conductive gate electrode and disposed within a first inter-level dielectric (ILD) layer over the PMD layer and the first gate structure.
2. The integrated chip of claim 1 ,
wherein the second gate structure is separated from the epitaxial source/drain region by a second gap; and
wherein the flowable dielectric material is disposed within the second gap.
3. The integrated chip of claim 2 , wherein the epitaxial source/drain region comprises an embedded silicon germanium region that is located between the first gate structure and the second gate structure.
4. The integrated chip of claim 1 , wherein the first gap has an aspect ratio between a height of the first gap and a width of the first gap, which is greater than 12:1.
5. The integrated chip of claim 1 , wherein the first gap has a sidewall angle, between the substrate and a sidewall of the epitaxial source/drain region, which is greater than 80°.
6. The integrated chip of claim 1 , wherein the flowable dielectric material comprises Trisilylamin.
7. The integrated chip of claim 1 , wherein the first gate structure further comprises:
a sidewall spacer arranged along opposing sides of the conductive gate electrode, wherein the sidewall spacer comprises a first sidewall facing the conductive gate electrode and a second sidewall contacting the PMD layer and the flowable dielectric material.
8. The integrated chip of claim 1 , wherein the PMD layer is in direct contact with upper surface of the flowable dielectric material and a lower surface of the first ILD layer.
9. The integrated chip of claim 1 , wherein the PMD layer comprises a boron-phosphor-silicate glass.
10. An integrated chip, comprising:
a source/drain region protruding outward from a semiconductor substrate;
a gate structure separated from the source/drain region by a gap;
a flowable dielectric material disposed within the gap;
a pre-metal dielectric (PMD) layer arranged over the flowable dielectric material, wherein the PMD layer has an upper surface that is substantially aligned with an upper surface of a conductive gate electrode within the gate structure; and
an inter-level dielectric (ILD) layer arranged over the PMD layer and the gate structure.
11. The integrated chip of claim 10 , wherein the gate structure further comprises:
a sidewall spacer located on opposing sides of the conductive gate electrode, wherein the sidewall spacer comprises a first sidewall facing the conductive gate electrode and a second sidewall contacting the PMD layer and the flowable dielectric material.
12. The integrated chip of claim 10 , further comprising:
a second gate structure separated from the source/drain region by a second gap, wherein the PMD layer continuously extends between the gate structure and the second gate structure.
13. The integrated chip of claim 10 , wherein the PMD layer is in direct contact with upper surface of the flowable dielectric material and with a lower surface of the ILD layer.
14. An integrated chip, comprising:
an epitaxial source/drain region protruding outward from a substrate;
a gate structure comprising a conductive gate electrode and a sidewall spacer, wherein the gate structure is separated from the epitaxial source/drain region by a gap;
a flowable dielectric material disposed within the gap;
a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material, wherein the sidewall spacer comprises a first sidewall contacting the conductive gate electrode and a second sidewall contacting the PMD layer and the flowable dielectric material; and
an inter-level dielectric (ILD) layer over the PMD layer and the gate structure.
15. The integrated chip of claim 14 , wherein the PMD layer has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode.
16. The integrated chip of claim 14 , wherein the PMD layer is in direct contact with upper surface of the flowable dielectric material and with a lower surface of the ILD layer.
17. The integrated chip of claim 14 , further comprising:
a metal contact extending from an upper surface of the ILD layer to a location in electrical contact with the conductive gate electrode.
18. The integrated chip of claim 14 , wherein the PMD layer has opposing outermost sidewalls that are aligned with opposing sidewalls of the flowable dielectric material.
19. The integrated chip of claim 14 , wherein the PMD layer is arranged over opposing sides of the epitaxial source/drain region.
20. The integrated chip of claim 1 , further comprising:
a sidewall spacer comprising a first sidewall contacting the conductive gate electrode and a second sidewall contacting the PMD layer and the flowable dielectric material.