IP Library › Granted Patent US 9,837,316
Granted Patent B2
US 9,837,316 · App. 15/367,568 · Granted Dec 5, 2017

Method of manufacturing thin film transistor, and method of manufacturing display apparatus

Inventors: Jongchan Lee (Yongin-si, KR); Yoonho Khang (Yongin-si, KR); Myounghwa Kim (Yongin-si, KR); Joonhwa Bae (Yongin-si, KR); Myounggeun Cha (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H01L21/823418H01L21/02422H01L21/02488H01L21/02532H01L21/02592H01L21/02667H01L21/02672H01L21/28518H01L21/32053H01L27/1222H01L27/1274H01L27/1277H01L29/41733H01L29/458H01L29/66765H01L29/78618H01L29/78678H01L27/3262
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Quick Facts
Patent No.
US 9,837,316
App. No.
15/367,568
Granted
Dec 5, 2017
Kind
B2
Abstract

A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.

Claims (23)

1. A method of manufacturing a thin film transistor (TFT), the method comprising:

forming an amorphous silicon layer on a substrate including a first area, a second area adjacent to one side of the first area, and a third area adjacent to another side of the first area;

disposing metal catalysts on an upper surface of the amorphous silicon layer;

forming a metal layer over the amorphous silicon layer and the metal catalysts in the second and third areas; and

transforming the amorphous silicon layer into a polysilicon layer and conditioning the metal layer to include a metal silicide layer using a heat treatment process.

2. The method as claimed in claim 1 , wherein forming the metal layer includes:

forming the metal layer to cover the amorphous silicon layer and the metal catalysts in the first through third areas; and

removing a portion of the metal layer in at least a portion of the first area.

3. The method as claimed in claim 2 , wherein removing the portion of the metal layer includes removing at least a portion of the metal catalysts between the metal layer and the amorphous silicon layer in the first area.

4. The method as claimed in claim 1 , wherein conditioning the metal layer includes transforming all portions of the metal layer into the metal silicide layer.

5. The method as claimed in claim 4 , further comprising:

forming an additional metal layer to contact the metal silicide layer.

6. The method as claimed in claim 5 , wherein forming the additional metal layer includes using a material identical to a material used in forming the metal layer.

7. The method as claimed in claim 5 , wherein forming the additional metal layer includes forming:

a first layer including a material identical to a material used in forming the metal layer, and

a second layer on the first layer, the second layer including a different material from the first layer.

8. The method as claimed in claim 1 , wherein conditioning the metal layer includes transforming a portion of the metal layer facing the amorphous silicon layer into the metal silicide layer, wherein a remaining portion of the metal layer remains as an additional metal layer.

9. The method as claimed in claim 1 , wherein forming the metal layer includes forming:

a first layer over the amorphous silicon layer and the metal catalysts in the second and third areas, and

a second layer on the first layer, wherein the second layer includes a material different from a material used to form the first layer.

10. The method as claimed in claim 9 , wherein conditioning the metal layer includes transforming a portion of the first layer facing the amorphous silicon layer into the metal silicide, wherein a remaining portion of the first layer and the second layer remains as an additional metal layer.

11. A method of manufacturing a display apparatus, the method comprising:

forming a thin film transistor (TFT) using the method as claimed in claim 1 ; and forming a display that is electrically connected to the TFT.

Priority Claims (1)
KR 10-2014-0101099 · Aug 6, 2014 · national
Continuity (2)
Division 14597563 · Jan 15, 2015
Related Publication 20170084755A1 · Mar 23, 2017