Semiconductor devices including source/drain regions having silicon carbon

1. A semiconductor device comprising:

a fin active region protruding from a substrate;

gate patterns on the fin active region, the gate patterns extending in a first direction over the fin active region including across a first sidewall of the fin active region to a second sidewall of the fin active region;

a source/drain region on the fin active region between the gate patterns; and

contact patterns on the source/drain region,

wherein the source/drain region comprises a wave-shaped upper surface with respect to a vertical cross-sectional view that is perpendicular to the first direction.

2. The semiconductor device of claim 1 , wherein the source/drain region comprises silicon carbon (SiC).

3. The semiconductor device of claim 1 , further comprising a capping source/drain region on the source/drain region.

4. The semiconductor device of claim 3 , wherein the capping source/drain region comprises epitaxially grown silicon (Si).

5. The semiconductor device of claim 3 , wherein the capping source/drain region has a substantially flat upper surface.

6. The semiconductor device of claim 3 , wherein the capping source/drain region has a curved upper surface.

7. The semiconductor device of claim 1 , wherein the contact pattern comprises:

a silicide layer on the source/drain region;

a contact barrier layer on the silicide layer; and

a contact plug on the contact barrier layer.

8. The semiconductor device of claim 7 , wherein:

the source/drain region comprises a recessed upper surface; and

the silicide layer is formed on the recessed upper surfaces of the source/drain region to have a bowl shape.

9. The semiconductor device of claim 7 , wherein the silicide layer of the contact pattern is in contact with the source/drain region.

10. A semiconductor device comprising:

a substrate provided with a fin active region;

gate patterns disposed on the fin active region;

a source/drain region protruding from the fin active region between the gate patterns; and

a contact pattern disposed on the source/drain region,

wherein the source/drain region comprises a lower source/drain region and a capping source/drain region disposed on the lower source/drain region, and

an interface between the lower source/drain region and the capping source/drain region has a wave shape.

11. The semiconductor device of claim 10 , wherein:

the lower source/drain region is disposed within a trench formed in the fin active region; and

the capping source/drain region is disposed on the lower source/drain region to protrude above the surface of the fin active region.

12. The semiconductor device of claim 10 , further comprising gate spacers disposed on sidewalls of the gate patterns,

wherein the capping source/drain region is in contact with the gate spacers.

13. The semiconductor device of claim 10 , wherein the interface comprises a protruding center portion, a recessed inner portion around the center portion, and an outer portion around the inner portion,

wherein the outer portion is located at a level lower than the center portion and higher than the inner portion.

14. The semiconductor device of claim 10 ,

wherein the gate patterns extend in a first direction over the fin active region including across a first sidewall of the fin active region to a second sidewall of the fin active region, and

wherein the interface between the lower source/drain region and the capping source/drain region has a wave shape with respect to a vertical cross-sectional view that is perpendicular to the first direction.

15. A semiconductor device comprising:

a substrate provided with fin active regions, the fin active regions extending parallel to each other;

gate patterns extending parallel to each other and crossing the fin active regions;

source/drain regions formed on the fin active regions in recesses in the fin active regions between the gate patterns; and

contact patterns disposed on the source/drain regions,

wherein the source/drain regions comprise:

lower source/drain regions disposed in the recesses of the fin active regions; and

upper source/drain regions disposed on the lower source/drain regions protruding above surfaces of the fin active regions,

wherein each lower source/drain regions comprises a protruding center portion and a recessed inner portion adjacent to a corresponding center portion.

16. The semiconductor device of claim 15 , wherein the contact patterns comprise:

silicide layers disposed on the upper source/drain regions;

contact barrier layers disposed on the silicide layers; and

contact plugs disposed on the contact barrier layers,

wherein the silicide layers and the contact barrier layers extend into the upper source/drain regions.

17. The semiconductor device of claim 16 , wherein the contact patterns are in contact with the lower source/drain regions.

18. The semiconductor device of claim 15 , wherein the gate patterns comprise:

interfacial insulating layers directly disposed on the fin active regions and having a sheet shaped cross section;

gate insulating layers disposed on the interfacial insulating layers and having a U-shaped cross section;

gate barrier layers directly disposed on the gate insulating layers and having a U-shaped cross section; and

gate electrodes disposed on the gate barrier layers.

19. The semiconductor device of claim 15 , wherein the center portions of the lower source/drain regions protrude over the fin active regions.

20. The semiconductor device of claim 15 ,

wherein the gate patterns extend in a first direction over the fin active regions including across a first sidewall to a second sidewall of each of the fin active regions, and

wherein each of the lower source/drain regions has a wave shape with respect to a vertical cross-sectional view that is perpendicular to the first direction.