Configurable gate array based on three-dimensional writable memory
View Patent ↗The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
1. A configurable gate array, comprising:
at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and
at least a first portion of a first configurable computing element formed in a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, wherein said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function.
2. The configurable gate array according to claim 1 , wherein said first 3D-W array at least partially covers said configurable logic element.
3. The configurable gate array according to claim 1 , further comprising at least a configurable interconnect formed on said semiconductor substrate.
4. The configurable gate array according to claim 1 , further comprising at least a multiplier formed on said semiconductor substrate.
5. The configurable gate array according to claim 1 , further comprising at least a second portion of a second configurable computing element formed in a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array is electrically programmable and can be loaded with a second LUT for a second math function.
6. The configurable gate array according to claim 1 , wherein said first 3D-W array is electrically re-programmable and said first configurable computing element can be re-configured to realize different math functions.
7. A configurable gate array, comprising:
at least a configurable interconnect formed on a semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and
at least a first portion of a first configurable computing element formed in a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, wherein said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function.
8. The configurable gate array according to claim 7 , wherein said first 3D-W array at least partially covers said configurable interconnect.
9. The configurable gate array according to claim 7 , further comprising at least a configurable logic element formed on said semiconductor substrate.
10. The configurable gate array according to claim 7 , further comprising at least a multiplier formed on said semiconductor substrate.
11. The configurable gate array according to claim 7 , further comprising at least a second portion of a second configurable computing element formed in a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array is electrically programmable and can be loaded with a second LUT for a second math function.
12. The configurable gate array according to claim 7 , wherein said first 3D-W array is electrically re-programmable and said first configurable computing element can be re-configured to realize different math functions.
13. A configurable gate array, comprising:
an array of configurable computing elements including a configurable computing element, wherein said configurable computing element is electrically programmable and can be loaded with a look-up table (LUT) for a math function;
an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;
an array of configurable interconnects including a configurable interconnect, wherein said array of configurable interconnects couple said array of configurable computing elements with said array of configurable logic elements;
wherein said configurable gate array realizes a complex math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects.
14. The configurable gate array according to claim 13 , wherein at least a portion of said configurable computing element is formed in a three-dimensional writable memory (3D-W) array stacked above a semiconductor substrate.
15. The configurable gate array according to claim 14 , wherein said configurable logic element is formed on said semiconductor substrate.
16. The configurable gate array according to claim 15 , wherein said 3D-W array at least partially covers said configurable logic element.
17. The configurable gate array according to claim 14 , wherein said configurable interconnect is formed on said semiconductor substrate.
18. The configurable gate array according to claim 17 , wherein said 3D-W array at least partially covers said configurable interconnect.
19. The configurable gate array according to claim 13 , further comprising at least one multiplier.
20. The configurable gate array according to claim 14 , wherein said 3D-W array is electrically re-programmable and said configurable computing element can be re-configured to realize different math functions.