CMOS sensor with standard photosites
View Patent ↗An image sensor having photosites forming an array (K×L) of K rows and L columns, including a first set of integrator circuits, with a first regulation by analog weighting in blocks of n×n′ photosites, said photosites belonging to n adjacent columns and to n′ adjacent rows, and a second set of integrator circuits, with a second regulation by analog weighting in blocks of m×m′ photosites, said photosites belonging to m adjacent columns and to m′ adjacent rows, n adjacent columns of a first set of columns of the array being connected to n×n′ integrator circuits of the first set, m adjacent columns of a second set of columns of the array being connected to m×m′ integrator circuits of the second set, n columns of the first set alternating with m columns of the second set to form the array of photosites.
1. An image sensor device, comprising a plurality of photosites forming an array (K×L) of K rows and L columns, and at least one analog-to-digital converter, each photosite being adapted to receive a luminous flux and to deliver an electrical signal, in analog form,
further comprising at least:
a first set of integrator circuits, with a first regulation by analog weighting in blocks of n×n′ photosites, said photosites belonging to n adjacent columns and to n′ adjacent rows, and
a second set of integrator circuits, with a second regulation by analog weighting in blocks of m×m′ photosites, said photosites belonging to m adjacent columns and to m′ adjacent rows,
n adjacent columns of a first set of columns of the array being connected to n×n′ integrator circuits of the first set,
m adjacent columns of a second set of columns of the array being connected to m×m′ integrator circuits of the second set,
n columns of the first set alternating with m columns of the second set to form the array of photosites;
the device comprising, in each of said first and second sets:
computing means suitable for delivering an analog signal corresponding to an average of the analog signals delivered by said blocks of n×n′ photosites and, respectively, by said blocks of m×m′ photosites, and
at least one regulation means for weighting an analog signal from each photosite by an average signal of a block to which the photosite belongs.
2. The device according to claim 1 , wherein the first set of integrator circuits is attached to a first end edge of said array, at the bottom of the columns, and the second set of integrator circuits is attached to a second end edge of said array, opposite to the first edge, at the top of the columns.
3. The device according to claim 1 , comprising at least as many regulation means as simultaneously read photosites and at least as many converters as simultaneously read photosites.
4. The device according to claim 1 , comprising fewer regulation means than simultaneously read photosites and fewer converters than simultaneously read photosites.
5. The device according to claim 4 , comprising a single regulation means and a single converter for the entire photosite array.
6. The device according to claim 1 , wherein said sets of integrator circuits are symmetrical on either side of the array.
7. The device according to claim 1 , wherein said first set of integrator circuits and said second set of integrator circuits operate in synchronization.
8. The device according to claim 1 , wherein n=m=n′=m′=2.
9. The device according to claim 1 , wherein said sets of integrator circuits further comprise at least one means for compensating for fixed pattern noise.
10. The device according to claim 1 , wherein said integrator circuits comprise at least one means for sampling and holding analog signals.