Non-volatile SRAM memory cell, and non-volatile semiconductor storage device
A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M 1 a or the second memory cell M 1 b . Thus memory capacity is increased.
1. A non-volatile SRAM memory cell comprising:
an SRAM comprising a first storage node and a second storage node complementary to the first storage node;
a plurality of non-volatile memory sections connected in parallel to the SRAM; and
a node controller connected to the SRAM and to the non-volatile memory sections,
each non-volatile memory section comprising:
a first memory cell configured to electrically connect a first memory to the first storage node through a first switch transistor; and
a second memory cell configured to electrically connect a second memory to the second storage node through a second switch transistor,
wherein the first switch transistor and the second switch transistor turn on or off separately from each other,
the node controller comprising:
a first node control transistor connected to the first storage node and to one end of the first switch transistor of each of the non-volatile memory sections;
a second node control transistor connected to the second storage node and to one end of the second switch transistor of each of the non-volatile memory sections;
a node control source line; and
a resistor element disposed between the first node control transistor and the node control source line and between the second node control transistor and the node control source line, the resistor element allowing a current higher than or equal to a specified value to flow,
wherein a first node control gate line is connected to the first node control transistor, and a second node control gate line is connected to the second node control transistor, and the first node control transistor and the second node control transistor are turned on or off separately from each other,
wherein the node controller performs a switching operation to selectively connect the first storage node and/or the second storage node to the node control source line.
2. The non-volatile SRAM memory cell according to claim 1 , wherein
a first switch gate line is connected to the first switch transistor, and
a second switch gate line is connected to the second switch transistor, and
the first switch transistor turns on or off in accordance with a voltage applied to a gate of the first switch transistor through the first switch gate line, and
the second switch transistor turns on or off in accordance with a voltage applied to a gate of the second switch transistor through the second switch gate line.
3. A non-volatile SRAM memory cell comprising:
an SRAM comprising a first storage node and a second storage node complementary to the first storage node;
a plurality of non-volatile memory sections connected in parallel to the SRAM; and
a node controller connected to the SRAM and to the non-volatile memory sections,
each non-volatile memory section comprising:
a first memory cell configured to electrically connect a first memory to the first storage node through a first switch transistor;
a second memory cell configured to electrically connect a second memory to the second storage node through a second switch transistor,
a first common switch transistor disposed between the first switch transistor and the first storage node, the first common switch transistor being connected in series to the first switch transistor; and
a second common switch transistor disposed between the second switch transistor and the second storage node, the second common switch transistor being connected in series to the second switch transistor,
wherein the first common switch transistor and the second common switch transistor turn on or off separately from each other,
the node controller comprising:
a first node control transistor connected to the first storage node;
a second node control transistor connected to the second storage node;
a node control source line; and
a resistor element disposed between the first node control transistor and the node control source line and between the second node control transistor and the node control source line, the resistor element allowing a current higher than or equal to a specified value to flow,
wherein a first node control gate line is connected to the first node control transistor, and a second node control gate line is connected to the second node control transistor, and the first node control transistor and the second node control transistor are turned on or off separately from each other,
wherein the node controller performs a switching operation to selectively connect the first storage node and/or the second storage node to the node control source line.
4. The non-volatile SRAM memory cell according to claim 1 , wherein one of the first switch transistor and the second switch transistor of a selected one of the non-volatile memory sections is turned on, to write one of non-volatile data of the first memory cell and non-volatile data of the second memory cell into the first or second storage node connected to the first or second switch transistor that is turned on.
5. The non-volatile SRAM memory cell according to claim 1 , wherein one of the first switch transistor and the second switch transistor of a selected one of the non-volatile memory sections is turned on, to establish electrical connection between the first storage node and the first memory or between the second storage node and the second memory, and SRAM data stored in one of the first storage node and the second storage node is programmed into the first memory cell or the second memory cell.
6. The non-volatile SRAM memory cell according to claim 1 , wherein one end of the first memory is connected to the first switch transistor and the other end of the first memory is connected to a memory source line, and one end of the second memory is connected to the second switch transistor and the other end of the second memory is connected to the memory source line, and
one of the first switch transistor and the second switch transistor is turned on to connect the memory source line to one of the first storage node and the second storage node, and non-volatile data in the first memory cell or non-volatile data in the second memory cell is erased by a potential difference between a voltage on the first or second storage node connected to the memory source line and a voltage on the memory source line.
7. A non-volatile SRAM memory cell comprising:
an SRAM comprising a first storage node and a second storage node complementary to the first storage node;
a plurality of non-volatile memory sections connected in parallel to the SRAM; and
a node controller connected to the SRAM and to the non-volatile memory sections,
each non-volatile memory section comprising:
a first memory cell configured to electrically connect a first memory to the first storage node through a first switch transistor; and
a second memory cell configured to electrically connect a second memory to the second storage node through a second switch transistor,
wherein the first switch transistor and the second switch transistor turn on or off separately from each other,
wherein one of the first switch transistor and the second switch transistor of a selected one of the non-volatile memory sections is turned on, to write one of non-volatile data of the first memory cell and non-volatile data of the second memory cell into the first or second storage node connected to the first or second switch transistor that is turned on, and
in a case where the non-volatile data of one of the first memory cell and the second memory cell is written into the SRAM, a first access transistor provided in the SRAM is turned off to disconnect electrical connection between the SRAM and a first bit line and a second access transistor provided in the SRAM is turned off to disconnect electrical connection between the SRAM and a second bit line, and
in a case where a memory current is higher than a reference current, a potential of the first or second storage node into which the non-volatile data is to be written is lower than a potential of the second or the first storage node to which the non-volatile data is not to be written, and
in a case where the memory current is lower than the reference current, the potential of the first or second storage node into which the non-volatile data is to be written is higher than the potential of the second or first storage node to which the non-volatile data is not to be written,
the memory current flowing to the first or second memory that writes the non-volatile data into the SRAM, from the first or second storage node into which the non-volatile data is to be written, the reference current flowing to the node controller from the second or first storage node into which the non-volatile data is not to be written.
8. A non-volatile SRAM memory cell comprising:
an SRAM comprising a first storage node and a second storage node complementary to the first storage node;
a plurality of non-volatile memory sections connected in parallel to the SRAM; and
a node controller connected to the SRAM and to the non-volatile memory sections,
each non-volatile memory section comprising:
a first memory cell configured to electrically connect a first memory to the first storage node through a first switch transistor; and
a second memory cell configured to electrically connect a second memory to the second storage node through a second switch transistor,
wherein the first switch transistor and the second switch transistor turn on or off separately from each other,
wherein the node controller performs a switching operation to selectively connect the first storage node and/or the second storage node to a node control source line, and
in a state that the electrical connection between the SRAM and the first bit line is disconnected by turning off the first access transistor provided in the SRAM and the electrical connection between the SRAM and the second bit line is disconnected by turning off the second access transistor provided in the SRAM, application of power supply voltage to the first and second storage nodes is stopped and the first and second storage nodes are connected to the node control source line through the node controller, to lower the potentials of the first storage node and the second storage node to potentials of an initial state.
9. A non-volatile semiconductor memory device comprising:
non-volatile SRAM memory cells according to claim 1 , the non-volatile SRAM memory cells disposed in a matrix of rows and columns, the non-volatile SRAM memory cells disposed on one side share a first bit line and a second bit line.