IP Library › Granted Patent US 9,842,785
Granted Patent B2
US 9,842,785 · App. 15/333,098 · Granted Dec 12, 2017

Apparatus and method for verification of bonding alignment

Inventors: Xin-Hua Huang (Xihu Township, TW); Ping-Yin Liu (Yonghe, TW); Lan-Lin Chao (Sindian, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L22/34H01L21/768H01L22/20H01L22/30H01L23/492H01L24/05H01L24/89H01L24/94H01L24/08H01L24/80H01L2224/0237H01L2224/05647H01L2224/08145H01L2224/802H01L2224/80011H01L2224/80013H01L2224/80075H01L2224/80121H01L2224/80203H01L2224/80894H01L2224/80895H01L2224/80896H01L2224/94
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,842,785
App. No.
15/333,098
Granted
Dec 12, 2017
Kind
B2
Abstract

Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.

Claims (27)

1. A device comprising:

a common node disposed in a first wafer;

a test node disposed in the first wafer and having a plurality of test pads exposed at a first surface of the first wafer, the test node further having a plurality of test node lines separated by a first spacing and exposed at a second surface of the first wafer and each connected to a respective one of the plurality of test pads; and

a comb disposed in a second wafer and having a plurality of comb lines having a second spacing different from the first spacing, each of the comb lines having a first surface exposed at a first side of the second wafer.

2. The device of claim 1 , wherein the common node includes a common node pad exposed at the first surface of the first wafer and further includes a plurality of common node lines exposed at the second surface of the first wafer, the common node lines being separated by the first spacing.

3. The device of claim 1 , wherein respective test node lines of the plurality of test node lines comprises substantially straight conductive line segments extending from the first surface of the first wafer to the second surface of the first wafer.

4. The device of claim 1 , wherein at least one test node line is aligned and in electrical contact with at least one comb line and wherein at least one comb line is misaligned with at least one test node line.

5. The device of claim 1 , wherein the comb is a Vernier-type comb.

6. The device of claim 5 , wherein the test node has a same number of test node lines as a number of comb lines.

7. The device of claim 5 , wherein the comb lines are arranged to have a single comb line aligning directly with a corresponding test line at predetermined alignment shifts.

8. The device of claim 1 , wherein the comb is a binary comb.

9. The device of claim 1 , wherein the comb lines are spaced laterally apart, and the first surface of each of the comb lines has a lateral width between about 0.005 μm and about 0.2 μm.

10. The device of claim 1 , wherein a portion of the test node and a portion of the common node are disposed in a redistribution layer (RDL) on the first wafer.

11. The device of claim 1 , wherein the comb is disposed in an RDL on the second wafer.

12. A device comprising:

a first wafer having a common node extending from a first side of the first wafer to a second side, the common node including a plurality of common node lines exposed at the second side of the first wafer, the first wafer further including a plurality of test node lines each test node line having a first end exposed at the first side of the first wafer and a second end exposed at the second side of the first wafer; and

a second wafer bonded to the first wafer, the second wafer having a comb including plurality of comb lines, each of the comb lines having a first end adjacent a corresponding common node line and a second end adjacent to a corresponding test node line.

13. The device of claim 12 , wherein at least one comb line is aligned with and in electrical contact with the corresponding common node line and the corresponding test node line.

14. The device of claim 12 , wherein the comb lines are configured to provide, at one of a plurality of predetermined alignment shifts, electrical connections between the common node and one or more test node lines when the first wafer is bonded to the second wafer.

15. The device of claim 12 , wherein the comb is a Vernier-type comb.

16. The device of claim 12 , wherein the comb is a binary comb.

17. The device of claim 12 , wherein the comb lines are spaced laterally apart, wherein the first end of each of the comb lines has a lateral width between about 0.005 μm and about 0.2 μm.

18. The device of claim 12 , wherein the comb lines are spaced laterally apart, wherein the test node lines have a first surface of the first end disposed at the first side of the second wafer, and wherein the first surface of each test node line has a lateral width of about 0.01 μm.

19. A method, comprising:

bonding a first wafer to a second wafer, the first wafer having therein a first conductive structure having a repeating pattern with a first pitch, the second wafer having therein a second conductive structure having a repeating pattern with a second pitch different than the first pitch; and

determining an alignment shift of the first wafer and the second wafer determining a number or arrangement of connections between the first conductive structure and the second conductive structure.

20. The method of claim 19 , wherein the second conductive structure is a Vernier-type comb, and wherein the determining the alignment shift comprises checking for an electrical connection between a common node of the first conductive structure and each of a plurality of test node lines of the second conductive structure, and determining the alignment shift based on which test node exhibits the electrical connection with the common node, or wherein the second conductive structure is a binary comb, and wherein the determining the alignment shift comprises checking for a combination of electrical connections between the common node and each of a plurality of test node lines and determining the alignment shift from the combination of electrical connections.

Continuity (2)
Continuation 14184402 · Feb 19, 2014
Related Publication 20170047260A1 · Feb 16, 2017