IP Library Granted Patent US 9,852,676
Granted Patent B2
US 9,852,676 · App. 15/114,152 · Granted Dec 26, 2017

Liquid crystal display device

Inventors: Hidekazu Miyata (Sakai, JP); Iori Aoyama (Sakai, JP); Yuichi Kita (Sakai, JP)
Assignee: Sharp Kabushiki Kaisha
G09G3/2018G02F1/1339G02F1/1368G02F1/13624G02F1/134309G02F1/134336G02F1/134363G02F1/136286G09G3/2003G09G3/3607G09G3/3614G09G3/3648G09G3/3685G09G3/3696G02F2001/134372G02F2201/123G09G2300/0426G09G2300/0434G09G2300/0443G09G2300/0465G09G2300/0478G09G2310/0235G09G2310/08G09G2320/0252G09G2320/0271G09G2320/0626
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Quick Facts
Patent No.
US 9,852,676
App. No.
15/114,152
Granted
Dec 26, 2017
Kind
B2
Abstract

An active matrix substrate ( 12 A) of a liquid crystal display device ( 10 ) includes: drive electrodes ( 32 A, 32 B) a pair of which are arranged in each pixel; pixel electrodes ( 36 ) each of which is provided in each pixel; first switching elements ( 34 A) each of which is connected to one of the pair of drive electrode ( 32 A); second switching elements ( 34 B) each of which is connected to the other drive electrode ( 32 B); third switching elements ( 34 C) connected to the pixel electrodes ( 36 ); first source lines ( 30 A) connected to the group of the first switching elements ( 34 ); second source lines ( 30 B) connected to the group of the second switching elements ( 34 B); third source lines ( 30 C) connected to the group of the third switching elements ( 30 C); and a plurality of gate lines ( 28 ).

Claims (42)

1. A liquid crystal display device comprising:

an active matrix substrate having a display region in which a plurality of pixel arrays are arranged, each pixel array being formed with a plurality of pixels aligned;

a counter substrate arranged so as to be opposed to the active matrix substrate; and

a crystal layer sealed between the active matrix substrate and the counter substrate,

wherein the active matrix substrate includes:

drive electrodes, a pair of which are arranged in each pixel on an insulating layer;

pixel electrodes, each of which is provided in each pixel on a side opposite to the pair of drive electrodes, with the insulating layer being interposed there between;

first switching elements, each of which is connected to one of the pair of drive electrodes in each pixel;

second switching elements, each of which is directly connected to the other of the pair of the drive electrodes in each pixel;

third switching elements, each of which is directly connected to the pixel electrode in each pixel;

first source lines, each of which is provided in each pixel array; the first source line being connected to a group of the first switching elements of a group of the pixels included in each pixel array;

second source lines, each of which is provided in each pixel array; the second source line being connected to a group of the second switching elements of the group of the pixels included in each pixel array;

third source lines, each of which is provided in each pixel array; the third source line being directly connected to a group of the third switching elements of the group of the pixels included in each pixel array; and

a plurality of gate lines, each of which supplies a control signal to the first switching element, the second switching element, and the third switching element of each pixel, and

the counter substrate includes a counter electrode arranged so as to be opposed to the pixel electrode and the pair of drive electrodes.

2. The liquid crystal display device according to claim 1 , further comprising:

a control unit that causes the display region to display an image,

wherein, with respect to each pixel, the control unit independently supplies a voltage corresponding to a gray level to be displayed on the pixel, via the first source line, the second source line, and the third source line, to the pair of drive electrodes and the pixel electrode.

3. The liquid crystal display device according to claim 2 ,

wherein the control unit includes a convertor that generates voltage values corresponding to voltages to be applied to the pair of drive electrodes and the pixel electrode in each pixel, based on a display gray level value indicating a gray level to be displayed on each pixel.

4. The liquid crystal display device according to claim 3 ,

wherein the control unit includes a conversion value recording section that records all gray level values that indicate all gray levels that can be displayed on the pixel, voltage values of the pair of drive electrodes corresponding to all the gray level values, and voltage values of the pixel electrode corresponding to all the gray level values, and

the convertor determines respective voltage values of the pair of drive electrodes corresponding to the display gray level value, and a voltage value of the pixel electrode corresponding to the display gray level value, by referring to the conversion value recording section.

5. The liquid crystal display device according to claim 3 , wherein the convertor includes:

a drive electrode voltage generation circuit that outputs a voltage value that serves as a reference value for the voltage values of the pair of drive electrodes corresponding to the display gray level value; and

a pixel electrode voltage generation circuit that outputs a voltage value that serves as a reference value for the voltage value of the pixel electrode corresponding to the display gray level value.

6. The liquid crystal display device according to claim 3 ,

wherein the convertor generates the voltage values in such a manner that at least one of the voltage value of one of the pair of drive electrodes, the voltage value of the other one of the pair of drive electrodes, and the voltage value of the pixel electrode is constant in a part of a range of all the gray levels that can be displayed by the pixel.

7. The liquid crystal display device according to claim 1 ,

wherein two of the first source lines, two of the second source lines, and two of the third source lines are provided for each pixel array,

the two first source lines in each pixel array are connected to two adjacent ones of the pixels in the pixel array, respectively, and voltages having different polarities are input simultaneously to the two first source lines, respectively,

the two second source lines in each pixel array are connected to two adjacent ones of the pixels in the pixel array, respectively, and voltages having different polarities are input simultaneously to the two second source lines, respectively, and

the two third source lines in each pixel array are connected to two adjacent ones of the pixels in the pixel array, respectively, and voltages having different polarities are input simultaneously to the two third source lines, respectively.

8. The liquid crystal display device according to claim 7 ,

wherein voltages having different polarities are simultaneously input to two adjacent lines, respectively, among the two first source lines, the two second source lines, and the two third source lines provided in each pixel array, and

voltages having different polarities are simultaneously input to the first source lines of two adjacent pixels, respectively, the two pixels being adjacent in a direction perpendicular to the direction in which the first source lines extend.

9. The liquid crystal display device according to claim 1 ,

wherein the control unit time-divides one frame period, and switches and displays images of different colors in each period thus time-divided.

10. The liquid crystal display device according to claim 1 ,

wherein the first switching element, the second switching element, and the third switching element are formed with thin film transistors,

each of the thin film transistors includes a semiconductor layer that includes an oxide semiconductor provided at a position opposed to the electrode connected to the gate line, a first electrode connected to one of the pair of drive electrodes or the pixel electrode, and a second electrode connected with the source line, and

the first electrode and the second electrode are formed so as to be separated from each other on the semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2016
From: MIYATA, HIDEKAZU; AOYAMA, IORI; KITA, YUICHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 039259/0616 →
Priority Claims (1)
JP 2014-015972 · Jan 30, 2014 · national
Continuity (1)
Related Publication 20170011680A1 · Jan 12, 2017