IP Library › Granted Patent US 9,852,968
Granted Patent B2
US 9,852,968 · App. 14/643,418 · Granted Dec 26, 2017

Semiconductor device including a sealing region

Inventor: Norihiro Nashida (Nagano, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/49811H01L23/10H01L23/16H01L23/3121H01L23/3135H01L23/3735H01L23/4334H01L23/49506H01L23/49575H01L23/49833H01L25/162H01L2224/48091H01L2924/1305H01L2924/13055H01L2924/13091
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Quick Facts
Patent No.
US 9,852,968
App. No.
14/643,418
Granted
Dec 26, 2017
Kind
B2
Abstract

The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate, a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and printed substrate, and a second sealing member that covers the whole excepting a bottom portion of the insulating substrate, the semiconductor device having sealing region regulation rod portions disposed in an outer peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and printed substrate, wherein the heat resistance temperature of the first sealing member is set to be higher than the heat resistance temperature of the second sealing member.

Claims (18)

1. A semiconductor device, comprising:

an insulating substrate on which is mounted a main circuit component including a semiconductor chip;

a printed substrate, opposing the insulating substrate, wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate;

a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and the printed substrate;

a second sealing member that covers the side surfaces, but not the bottom surface, of the insulating substrate, the side surfaces of the first sealing member, and the side surfaces and upper surface of the printed substrate; and

a sealing region regulation rod portions disposed in an outermost side peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and the printed substrate, the sealing region regulation rod portions being disposed such that they do not penetrate the second sealing member, wherein

the heat resistance temperature of the first sealing member is higher than the heat resistance temperature of the second sealing member.

2. The semiconductor device according to claim 1 , wherein the sealing region regulation rod portions are disposed in corner portions regulating the outer peripheral portion of the sealing region of the first sealing member.

3. The semiconductor device according to claim 1 , wherein the sealing region regulation rod portions support the liquid first sealing member using a surface tension thereof.

4. The semiconductor device according to claim 1 , wherein the sealing region of the first sealing member is set to be smaller than the outer peripheries of the insulating substrate and the printed substrate.

5. The semiconductor device according to claim 1 , wherein the sealing region regulation rod portions are formed of a member having high wettability with respect to the first sealing member.

6. The semiconductor device according to claim 1 , wherein the sealing region regulation rod portions are fitted into and held in fitting holes formed in the insulating substrate.

7. The semiconductor device according to claim 1 , wherein the sealing region regulation rod portions are formed of conductors that electrically connect a conductor pattern of the insulating substrate and a conductor pattern of the printed substrate.

8. The semiconductor device according to claim 1 , wherein the sealing region regulation rod portions are formed of an insulating resin having high wettability with respect to the first sealing member.

9. The semiconductor device according to claim 1 , wherein the sealing region of the first sealing member is disposed for each semiconductor chip when a plurality of the semiconductor chip are disposed.

10. The semiconductor device according to claim 1 , wherein a disposition interval of the sealing region regulation rod portions is set in accordance with a surface tension of the first sealing member.

11. The semiconductor device according to claim 1 , wherein an inlet through which the first sealing member is injected between the insulating substrate and the printed substrate is formed in either one of the insulating substrate and the printed substrate.

12. The semiconductor device according to claim 1 , wherein the semiconductor chip is a power semiconductor element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2015
From: NASHIDA, NORIHIRO
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 035128/0402 →
Priority Claims (1)
JP 2012-287754 · Dec 28, 2012 · national
Continuity (2)
Continuation PCTJP2013006591 · Nov 8, 2013
Related Publication 20150187689A1 · Jul 2, 2015