Semiconductor packages having through electrodes and methods of fabricating the same
Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.
1. A semiconductor device comprising:
a first semiconductor package comprising:
a first chip comprising a first active layer provided on a first side of the first chip;
a second chip comprising:
first through-electrodes; and
a second active layer provided on a second side of the second chip, the first chip and the second chip being stacked and the first active layer facing the second active layer; and
a mold layer disposed between the first chip and the second chip; and
a second semiconductor package comprising:
a third chip comprising:
second through-electrodes;
a third active layer provided on a third side of the third chip; and
a fourth chip comprising a fourth active layer provided on a fourth side of the fourth chip, the third chip and the fourth chip being stacked and the third active layer facing the fourth active layer;
wherein a fifth side of the third chip, opposite to the third side of the third chip, is configured to face a sixth side of the second chip opposite to the second side of the second chip,
wherein the third chip has a first width and the second chip has a second width that is larger than the first width,
wherein in the first semiconductor package, no additional chip is provided between the first chip and the second chip, and
wherein the fourth chip has a third width that is smaller than the first width of the third chip.
2. The semiconductor device of claim 1 , wherein the first chip further comprises third through-electrodes.
3. The semiconductor device of claim 2 further comprising a plurality of electrodes which connect the first through-electrodes and the second through-electrodes.
4. A semiconductor device comprising:
a first semiconductor package comprising:
a first chip comprising:
a first active layer provided on a first side of the first chip; and
first through-electrodes;
a second chip comprising:
a second active layer provided on a second side of the second chip; and
second through-electrodes, the first chip and the second chip being stacked and the first active layer facing the second active layer; and
a mold layer disposed between the first chip and the second chip; and
a second semiconductor package comprising:
a third chip comprising:
a third active layer provided on a third side of the third chip; and
third through-electrodes; and
a fourth chip comprising a fourth active layer provided on a fourth side of the fourth chip, the third chip and the fourth chip being stacked and the third active layer facing the fourth active layer;
wherein a fifth side of the third chip, opposite to the third side of the third chip, is configured to face a sixth side of the second chip opposite to the second side of the second chip, wherein the semiconductor device further comprises a plurality of electrodes which connect the second through-electrodes and the third through-electrodes,
wherein the first chip has a first width and the second chip has a second width that is longer than the first width, and
wherein the fourth chip has a fourth width and the third chip has a third width that is longer than the fourth width.
5. The semiconductor device of claim 1 , wherein a coefficient of thermal expansion (CTE) of a substrate of the second chip and a CTE of the mold layer are within an order of magnitude.
6. The semiconductor device of claim 1 , wherein a ratio of a coefficient of thermal expansion (CTE) of a substrate of the second chip and a CTE of the mold layer is in a range from 1 to 3.
7. The semiconductor device of claim 1 further comprising first connection electrodes electrically connecting the first active layer and the second active layer.
8. A semiconductor device comprising:
a first semiconductor package comprising:
a first chip comprising:
a first active layer provided on a first side of the first chip; and
first through-electrodes;
a second chip being stacked on the first chip and comprising:
a second active layer provided on a second side of the second chip; and
second through-electrodes; and
a mold layer disposed between the first chip and the second chip; and
a second semiconductor package comprising:
a third chip comprising a third active layer provided on a third side of the third chip; and
a fourth chip comprising a fourth active layer provided on a fourth side of the fourth chip, the fourth chip being stacked on the third chip;
wherein a fifth side of the third chip, opposite to the third side of the third chip, is configured to face a sixth side of the second chip, opposite to the second side of the second chip,
wherein the semiconductor device further comprises a plurality of electrodes which connect the second through electrodes and third through electrodes,
wherein the first chip has a first width and the second chip has a second width that is longer than the first width, and
wherein the fourth chip has a fourth width and the third chip as a third width that is longer than the fourth width.
9. The semiconductor device of claim 1 , wherein the fourth chip comprises a non-through via semiconductor chip.