Thin film transistor array substrate

1. A thin film transistor array substrate, comprising:

a substrate;

a plurality of pixel elements arranged on the substrate, each of the pixel elements comprising a thin film transistor and a pixel electrode electrically connected with a drain/source of the thin film transistor;

a light shielding electrode disposed between the substrate and the thin film transistor and configured to shield a channel of the thin film transistor; wherein the light shielding electrode comprises a transparent electrically-conductive layer and a non-transparent electrically-conductive layer stacked on top of each other;

a storage capacitor comprising a first electrode and a second electrode disposed opposite to each other, the [A&B1] first electrode of the storage capacitor being located in a same layer as the transparent electrically-conductive layer of the light shielding electrode, wherein the first electrode of the storage capacitor is formed of transparent electrically-conductive material;

a common electrode;

wherein a potential of the first electrode is the same as a potential of the common electrode; and

a peripheral drive circuit, comprising a peripheral transparent electrically-conductive layer, a first connection metal, a second connection metal,

wherein the first connection metal and the common electrode are electrically connected and have the same potential,

wherein the second connection metal and the first connection metal are electrically connected,

wherein the second connection metal and the peripheral transparent electrically-conductive layer are electrically connected,

wherein the peripheral transparent electrically-conductive layer and the first electrode of the storage capacitor are electrically connected, and

wherein the peripheral drive circuit provides a potential to the first electrode of the storage capacitor.

2. The thin film transistor array substrate according to claim 1 , wherein the first electrode of the storage capacitor is formed by a same material as the transparent electrically-conductive layer of the light shielding electrode.

3. The thin film transistor array substrate according to claim 2 , further comprises:

a first insulation layer on the light shielding electrode and the first electrode of the storage capacitor;

an active layer on the first insulation layer and the light shielding electrode;

a second insulation layer on the active layer; and

a source electrode and a drain electrode on the second insulation layer and electrically connected with the active layer each through a via traversing the second insulation layer.

4. The thin film transistor array substrate according to claim 3 , wherein the second electrode of the storage capacitor is disposed in a same layer and of a same material as the source electrode and the drain electrode.

5. The thin film transistor array substrate according to claim 3 , wherein the second electrode of the storage capacitor is disposed in a same layer and of a same material as the active layer.

6. The thin film transistor array substrate according to claim 3 , wherein the thin film transistor further comprises a top gate disposed above the channel.

7. The thin film transistor array substrate according to claim 6 , wherein the second electrode of the storage capacitor is disposed in a same layer and of a same material as the top gate.

8. The thin film transistor array substrate according to claim 3 , wherein the light shielding electrode is a bottom gate of the thin film transistor.

9. The thin film transistor array substrate according to claim 3 , the active layer is electrically connected with the source electrode and the drain electrode through the vias in the second insulating layer and a conductive etching stopper layer.

10. A display panel, comprising the thin film transistor array substrate according to claim 1 .