Embedded source or drain region of transistor with downward tapered region under facet region

1. A Field Effect Transistor (FET) structure, comprising:

a body structure;

dielectric structures having a first pair of downward tapered side walls;

a gate structure formed over the body structure; and

a source or drain region which is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure,

wherein the source or drain region contains stressor material with a lattice constant different from that of the body structure; and

the source or drain region comprises:

a first region formed above a first level at a top of the dielectric structures; and

a second region that comprises a second pair of downward tapered side walls formed under the first level, formed on opposite sides of the body structure along a width of the body structure and abutting the first pair of downward tapered side walls of the dielectric structures.

2. The FET structure of claim 1 , wherein the body structure is a fin structure;

the gate structure wraps around a channel region of the body structure;

a first surface is leveled with a bottom of the gate structure; and

the dielectric structures are fin spacers formed above the first surface.

3. The FET structure of claim 2 , wherein one of the fin spacers is thicker towards the first surface and thinner away from the first surface.

4. The FET structure of claim 3 , wherein a thickness of the one of the fin spacers at the first surface has a range of about 0.1 nm to about 200 nm.

5. The FET structure of claim 2 , wherein a height of one of the fin spacers has a range of about 0.1 nm to about 200 nm.

6. The FET structure of claim 1 , wherein a first surface is leveled with a bottom of the gate structure;

one of the second pair of downward tapered side walls of the second region has an angle internal to the second region and with respect to the first surface; and

the angle is below about 160 degrees.

7. A Field Effect Transistor (FET) structure, comprising:

a body structure;

fin spacers;

a gate structure formed over the body structure; and

a source or drain region which is embedded in the body structure beside the gate structure, and abuts and is extended beyond the body structure,

wherein the source or drain region contains stressor material with a lattice constant different from that of the body structure; and

the source or drain region comprises:

a first region that comprises facets; and

a second region that comprises downward tapered sidewalls under the first region;

wherein the fin spacers abut the second region in between the fin spacers.

8. The FET structure of claim 7 , wherein the body structure is a fin structure;

the gate structure wraps around a channel region of the body structure; and

a first surface is leveled with a bottom of the gate structure;

wherein the fin spacers are formed above the first surface.

9. The FET structure of claim 8 , wherein one of the fin spacers is thicker towards the first surface and thinner away from the first surface.

10. The FET structure of claim 9 , wherein a thickness of the one of the fin spacers at the first surface has a range of about 0.1 nm to about 200 nm.

11. The FET structure of claim 9 , wherein a height of the one of the fin spacers has a range of about 0.1 nm to about 200 nm.

12. The FET structure of claim 7 , wherein a first surface is leveled with a bottom of the gate structure;

one of the downward tapered side walls of the second region has an angle internal to the second region and with respect to the first surface; and

the angle is below about 160 degrees.

13. A semiconductor structure, comprising:

a substrate;

a fin structure formed in and extended beyond the substrate;

dielectric structures;

an epitaxial region embedded in the fin structure, abutting the fin structure extended beyond the substrate, and extended beyond the dielectric structure;

wherein the epitaxial region contains stressor material with a lattice constant different from that of the fin structure; and

the epitaxial region comprises:

a first region formed above a first level at a top of the dielectric structures; and

a second region that comprises downward tapered side walls;

wherein the downward tapered side walls are formed on opposite sides of the fin structure along a width of the fin structure, formed under the first level and formed in between the dielectric structures.

14. The semiconductor structure of claim 13 , wherein the fin structure is a body structure;

a gate structure wraps around a channel region of the body structure; and

the epitaxial region is a source or drain region abutting the channel region.

15. The semiconductor structure of claim 13 , wherein the dielectric structures are formed over the substrate.

16. The semiconductor structure of claim 15 , wherein one of the dielectric structures is thicker towards the substrate and thinner away from the substrate.

17. The semiconductor structure of claim 16 , wherein a thickness of the one of the dielectric structures at a level of the one of the dielectric structures closest to the substrate has a range of about 0.1 nm to about 200 nm.

18. The semiconductor structure of claim 16 , wherein a height of the one of the dielectric structures has a range of about 0.1 nm to about 200 nm.

19. The semiconductor structure of claim 13 , wherein one of the downward tapered side walls of the second region has an angle internal to the second region with respect to a plane at a level of the one of the downward tapered side walls closest to the substrate; and

the angle is below about 160 degrees.

20. The semiconductor structure of claim 13 , wherein the first region is a facet region.