Semiconductor device and method for writing thereto
A semiconductor device ( 1001 ) includes: a memory cell; and a writing control circuit ( 107 ), wherein the memory cell includes a memory transistor ( 10 A) which has an active layer ( 7 A), the active layer ( 7 A) including a metal oxide, the memory transistor ( 10 A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit ( 107 ) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor ( 10 A) and Vds is a drain-source voltage of the memory transistor ( 10 A), whereby writing in the memory transistor ( 10 A) is performed.
1. A semiconductor device comprising:
at least one memory cell; and
a writing control circuit which controls writing in the at least one memory cell, wherein
the at least one memory cell includes a memory transistor which has an active layer, the active layer including a metal oxide,
the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs,
the writing control circuit is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode of the memory transistor such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor and Vds is a drain-source voltage of the memory transistor, whereby writing in the memory transistor is performed,
the at least one memory cell is one of a plurality of memory cells,
the plurality of memory cells include a memory cell which includes a memory transistor S in the semiconductor state and a memory cell which includes a memory transistor R in the resistor state,
the metal oxide includes a first metal element, and
the active layer of the memory transistor R includes a larger amount of the first metal element in a metal state than the active layer of the memory transistor S.
2. The semiconductor device of claim 1 , wherein
the memory transistor includes a gate electrode, the active layer, a first insulating layer provided between the gate electrode and the active layer, and a second insulating layer located on an opposite side from the first insulating layer,
the second insulating layer is in contact with a surface of the active layer, and
the first metal element in the metal state is present at an interface between the active layer and the second insulating layer.
3. The semiconductor device of claim 1 , wherein the first metal element in the metal state is present inside the active layer.
4. The semiconductor device of claim 1 , wherein
the metal oxide includes at least In, and
the first metal element in the metal state is In.
5. A semiconductor device comprising:
at least one memory cell; and
a writing control circuit which controls writing in the at least one memory cell, wherein
the at least one memory cell includes a memory transistor which has an active layer, the active layer including a metal oxide,
the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs,
the writing control circuit is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode of the memory transistor such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor and Vds is a drain-source voltage of the memory transistor, whereby writing in the memory transistor is performed,
the at least one memory cell is one of a plurality of memory cells,
the plurality of the memory cells include a memory cell which includes a memory transistor S in the semiconductor state and a memory cell which includes a memory transistor R in the resistor state, and
the active layer of the memory transistor R includes a larger number of voids than the active layer of the memory transistor S.
6. The semiconductor device of claim 5 , wherein the active layer of the memory transistor R includes a void which is present near the drain electrode.
7. A semiconductor device comprising:
at least one memory cell; and
a writing control circuit which controls writing in the at least one memory cell, wherein
the at least one memory cell includes a memory transistor which has an active layer, the active layer including a metal oxide,
the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs,
the writing control circuit is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode of the memory transistor such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor and Vds is a drain-source voltage of the memory transistor, whereby writing in the memory transistor is performed,
the at least one memory cell is one of a plurality of memory cells,
the plurality of memory cells include a memory cell which includes a memory transistor S in the semiconductor state and a memory cell which includes a memory transistor R in the resistor state, and
a channel region in the active layer of the memory transistor R and a channel region in the active layer of the memory transistor S have different compositions of the metal oxide.
8. The semiconductor device of claim 7 , wherein
the active layer includes a first metal element and a second metal element,
the first metal element has a higher standard electrode potential than that of the second metal element, and
a content rate of the second metal element in an ionic state to a total metal element in an ionic state which is included in the active layer of the memory transistor R is greater than a content rate of the second metal element in an ionic state to a total metal element in an ionic state which is included in the active layer of the memory transistor S.
9. The semiconductor device of claim 7 , wherein
the active layer includes a first metal element and a second metal element,
the first metal element has a higher standard electrode potential than that of the second metal element, and
a content rate of the first metal element in an ionic state to a total metal element in an ionic state which is included in the active layer of the memory transistor R is smaller than a content rate of the first metal element in an ionic state to a total metal element in an ionic state which is included in the active layer of the memory transistor S.
10. The semiconductor device of claim 8 , wherein
the metal oxide includes at least In and Ga, and
the first metal element is In and the second metal element is Ga.
11. The semiconductor device of claim 1 , wherein the metal oxide includes In, Ga, and Zn.
12. The semiconductor device of claim 11 , wherein the metal oxide includes a crystalline portion.
13. An electronic device comprising the semiconductor device as set forth in claim 1 .
14. The semiconductor device of claim 5 , wherein the metal oxide includes In, Ga, and Zn.
15. The semiconductor device of claim 14 , wherein the metal oxide includes a crystalline portion.
16. An electronic device comprising the semiconductor device as set forth in claim 5 .
17. The semiconductor device of claim 7 , wherein the metal oxide includes In, Ga, and Zn.
18. The semiconductor device of claim 17 , wherein the metal oxide includes a crystalline portion.
19. An electronic device comprising the semiconductor device as set forth in claim 7 .