3D memory process and structures

1. A method of fabricating a semiconductor device, the method comprising:

providing a substrate, the substrate having:

an array region of the substrate, the array region of the substrate having a first height, the first height being a height between a top surface and bottom surface of the substrate in the array region;

a peripheral region of the substrate, the peripheral region of the substrate having a second height greater than the first height, the second height being a height between a top surface and bottom surface of the substrate in the peripheral region; and

a border region of the substrate, the border region of the substrate separating the array region of the substrate from the peripheral region of the substrate, the border region of the substrate adjoining the array region of the substrate and the peripheral region of the substrate;

forming a plurality of alternating insulative and polysilicon layers over at least a portion of the top surface of the array region of the substrate and a top surface of the border region of the substrate;

forming a trench in the border region, the trench formed by removing at least a portion of the plurality of alternating insulative and polysilicon layers formed in the border region, the removing performed in such a way that a top surface of the trench resulting after the removing is lower in height than the second height, the trench formed substantially parallel to the border region of the substrate in such a way as to separate the array region of the substrate from the peripheral region of the substrate, the trench having sloping sidewalls; and

forming a plurality of memory cells over the array region of the substrate.

2. The method of claim 1 , wherein the border region comprises a steep step connecting a surface of the array region with a surface of the peripheral region, and the plurality of alternating insulative and polysilicon layers is formed over at least a portion of the sidewall of the steep step.

3. The method of claim 2 , wherein the trench through the plurality of alternating insulative and polysilicon layers is formed by placing a photoresist over the array region and at least a portion of the border region.

4. The method of claim 3 , wherein a gap formed between an edge of the photoresist and an outer surface of the plurality of alternating insulative and polysilicon layers formed over the sidewall of the steep step is less than about 3 microns.

5. The method of claim 3 , wherein a gap formed between an edge of the photoresist and an outer surface of the plurality of alternating insulative and polysilicon layers formed over the sidewall of the steep step is about 120 nm to 380 nm.

6. The method of claim 1 , further comprising forming a dielectric layer over at least a portion of the trench, wherein the forming the dielectric layer over at least a portion of the trench includes forming the dielectric layer over at least a portion of the sloping sidewalls of the trench.

7. The method of claim 6 , wherein the dielectric layer comprises nitride oxide layer.

8. The method of claim 5 , further comprising filling the trench with a second dielectric material.

9. A semiconductor device comprising:

a substrate, the substrate having:

an array region of the substrate, the array region of the substrate having a first height, the first height being a height between a top surface and bottom surface of the substrate in the array region;

a peripheral region of the substrate, the peripheral region of the substrate having a second height greater than the first height, the second height being a height between a top surface and bottom surface of the substrate in the peripheral region; and

a border region of the substrate, the border region of the substrate separating the array region of the substrate from the peripheral region of the substrate, the border region of the substrate adjoining the array region of the substrate and the peripheral region of the substrate;

a plurality of alternating insulative and polysilicon layers formed over at least a portion of the top surface of the array region of the substrate and a top surface of the border region of the substrate;

a trench formed in the border region, the trench formed by removing at least a portion of the plurality of alternating insulative and polysilicon layers formed in the border region, the removing performed in such a way that a top surface of the trench resulting after the removing is lower in height than the second height, the trench formed substantially parallel to the border region of the substrate in such a way as to separate the array region of the substrate from the peripheral region of the substrate, the trench having sloping sidewalls; and

a plurality of memory cells formed over the array region of the substrate.

10. The semiconductor device of claim 9 , wherein the border region comprises a steep step connecting a surface of the array region with a surface of the peripheral region, and the plurality of alternating insulative and polysilicon layers is formed over at least a portion of the sidewall of the steep step.

11. The semiconductor device of claim 9 , wherein a distance between peripheral edges of the trench is less than about 3 microns.

12. The semiconductor device of claim 9 , wherein a distance between peripheral edges of the trench is about 120 nm to 380 nm.

13. The semiconductor device of claim 9 , further comprising forming a dielectric layer over at least a portion of the trench, wherein the dielectric layer is formed over at least a portion of the sloping sidewalls of the trench.

14. The semiconductor device of claim 13 , wherein the dielectric layer comprises nitride oxide layer.

15. The semiconductor device of claim 13 , further comprising a second dielectric material in the trench.