Method for silicide formation

1. A method comprising:

forming a contact region on a substrate;

forming a dielectric layer over the contact region and the substrate;

forming an opening through the dielectric layer to expose a portion of the contact region;

forming a silicon-containing capping layer along the exposed portion of the contact region, sidewalls of the opening, and over the dielectric layer;

forming a metal layer over the silicon-containing capping layer in the opening and over the dielectric layer;

performing a silicidation process to react at least portions of the silicon-containing capping layer and the metal layer to form a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening, the silicidation process consuming at least a portion of the contact region; and

filling the opening over the metal-silicide layer with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

2. The method of claim 1 further comprising:

planarizing the conductive material to form the conductive plug, wherein after the planarizing step a top surface of the conductive plug is coplanar with a top surface of the dielectric layer.

3. The method of claim 1 , where the substrate is a semiconductor fin for a fin field-effect transistor (FinFET) and the contact region is a source/drain region for the FinFET, and wherein the forming the contact region comprises:

etching a recess in semiconductor fin;

epitaxially growing a semiconductor material in the recess; and

doping the semiconductor material with at least one dopant to form a source/drain region.

4. The method of claim 1 , wherein the contact region comprises silicon, silicon germanium, silicon phosphide, silicon carbide, or a combination thereof.

5. The method of claim 1 , wherein the silicon-containing capping layer comprises silicon, germanium, silicon germanium, silicon carbide, silicon phosphide, or a combination thereof.

6. The method of claim 1 , wherein the metal layer comprises nickel, cobalt, titanium, tungsten, or a combination thereof.

7. The method of claim 1 , wherein the metal-silicide layer extends along the sidewalls of the opening from a top surface of the contact region to a top surface of the dielectric layer.

8. The method of claim 1 , wherein the metal-silicide layer has a first thickness along the contact region and a second thickness along the sidewalls of the opening, the first thickness being greater than the second thickness.

9. The method of claim 8 , wherein the first thickness is from about 30 Angstroms (Å) to about 300 Å and the second thickness is from about 3 Å to about 30 Å.

10. The method of claim 1 further comprising:

before performing the silicidation process, forming a glue layer over the metal layer in the opening and over the dielectric layer.

11. The method of claim 1 , wherein the silicon-containing capping layer has a same material composition as the contact region.

12. A method comprising:

forming a source/drain region of a field-effect transistor (FET) on a semiconductor substrate;

depositing a dielectric layer over the source/drain region and the semiconductor substrate;

patterning the dielectric layer to form an opening through the dielectric layer, at least a portion of the source/drain region being exposed in the opening;

depositing a capping layer in the opening along the exposed portion of the source/drain region and sidewalls of the dielectric layer and over the dielectric layer;

depositing a metal layer over the capping layer in the opening and over the dielectric layer;

annealing the capping layer and the metal layer to form a metal-silicide layer in the opening along the source/drain region and the sidewalls of the dielectric layer and over the dielectric layer; and

after forming the metal-silicide layer, filling a conductive material over metal-silicide layer in the opening and over the dielectric layer.

13. The method of claim 12 , wherein the forming the source/drain region comprises:

etching a recess in the semiconductor substrate;

epitaxially growing a semiconductor material in the recess; and

doping the semiconductor material with at least one dopant to form the source/drain region.

14. The method of claim 12 further comprising:

before annealing the capping layer and the metal layer, forming a glue layer over the metal layer in the opening and over the dielectric layer.

15. A method comprising:

forming a dielectric layer over a substrate;

forming an opening in the dielectric layer to expose a first portion of a surface of the substrate;

depositing a silicon-containing capping layer along the exposed first portion of the surface of the substrate and sidewalls of the opening;

depositing a metal layer over the silicon-containing capping layer in the opening;

depositing a glue layer over the metal layer in the opening;

after depositing the glue layer, annealing the silicon-containing capping layer and the metal layer to form a metal-silicide layer in the opening along the first portion of the surface of the substrate and the sidewalls of the dielectric layer; and

filling a conductive material in the opening over the glue layer and over the dielectric layer.

16. The method of claim 15 , wherein after the annealing the silicon-containing capping layer and the metal layer to form the metal-silicide layer, a portion of the metal layer remains unreacted and is interposed between the metal-silicide layer and the glue layer.

17. The method of claim 15 , wherein the silicon-containing capping layer has a same material composition as the first portion of the surface of the substrate.

18. The method of claim 15 , wherein the metal-silicide layer has a surface extending below a topmost surface of the substrate.

19. The method of claim 15 , wherein the silicon-containing capping layer comprises silicon, germanium, silicon germanium, silicon carbide, silicon phosphide, or a combination thereof.

20. The method of claim 15 , wherein the glue layer comprises titanium nitride, tantalum nitride, or a combination thereof.