Optimized flash memory device for miniaturized devices
An implantable medical device have an associated memory device is disclosed. The implantable medical device utilizes techniques for optimizing one or more embedded operations of the memory device, such operations including programming, reading or erasing data. The techniques for optimizing the embedded operations include controlling the operations as a function of an energy source of the implantable medical device.
1. A method of programming a memory device of an implantable medical device, comprising:
computing, by one or more processors of the implantable medical device, a parameter of a battery of the implantable medical device;
erasing, by the one or more processors, a memory sector of the memory device;
determining, by the one or more processors, a programming delay based on a function of the computed parameter of the battery;
performing, by the one or more processors, an iterative programming of a plurality of elements in the memory sector; and
applying, by the one or more processors, the programming delay between programming of each consecutively programmed element of the plurality of elements during the iterative programming of the plurality of elements.
2. The method of claim 1 , wherein a value of the programming delay is defined as a function of the parameter of the battery.
3. The method of claim 1 , wherein the computed parameter is a remaining amount of energy stored by the battery.
4. The method of claim 1 , wherein the programming delay is a duration between a programming of data to a first memory element of the plurality of elements in the memory sector and a programming of data to a second memory element of the plurality of elements in the memory sector.
5. The method of claim 1 , further comprising receiving a memory address designator indicating the memory sector to be programmed.
6. The method of claim 1 , wherein a value of the programming delay increases as a remaining amount of energy stored by the battery decreases.
7. One or more processors of an implantable medical device configured to:
compute a parameter of a battery of the implantable medical device;
erase a memory sector of the memory device;
determine a programming delay based on a function of the computed parameter of the battery;
perform an iterative programming of a plurality of elements in the memory sector; and
apply the programming delay between programming of each consecutively programmed element of the plurality of elements during the iterative programming of the plurality of elements.
8. The one or more processors of claim 7 , wherein a value of the programming delay is defined as a function of the parameter of the battery.
9. The one or more processors of claim 7 , wherein the computed parameter is a remaining amount of energy stored by the battery.
10. The one or more processors of claim 7 , wherein the one or more processors are further configured to receive a memory address designator indicating the memory sector to be programmed.
11. The one or more processors of claim 7 , wherein a value of the programming delay increases as a remaining amount of energy stored by the battery decreases.
12. The one or more processors of claim 7 , wherein the programming delay is a duration between a programming of data to a first memory element of the plurality of elements in the memory sector and a programming of data to a second memory element of the plurality of elements in the memory sector.
13. A non-transitory computer-readable medium comprising instructions that, when executed, cause one or more processors of an implantable medical device to:
compute a parameter of a battery of the implantable medical device;
erase a memory sector of the memory device;
determine a programming delay based on a function of the computed parameter of the battery;
perform an iterative programming of a plurality of elements in the memory sector; and
apply the programming delay between programming of each consecutively programmed element of the plurality of elements during the iterative programming of the plurality of elements.
14. The computer-readable medium of claim 13 , wherein a value of the programming delay is defined as a function of the parameter of the battery.
15. The computer-readable medium of claim 13 , wherein the computed parameter is a remaining amount of energy stored by the battery.
16. The computer-readable medium of claim 13 , wherein the instructions further cause the one or more processors to receive a memory address designator indicating the memory sector to be programmed.
17. The computer-readable medium of claim 13 , wherein a value of the programming delay increases as a remaining amount of energy stored by the battery decreases.
18. The computer-readable medium of claim 13 , wherein the programming delay is a duration between a programming of data to a first memory element of the plurality of elements in the memory sector and a programming of data to a second memory element of the plurality of elements in the memory sector.