Methods of operating memory systems for sub-block erase operation
A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.
1. A method of operating a memory system including a memory block having a first sub-block having first word lines and a second sub-block having second word lines, the method comprising:
performing a first program operation on first memory cells connected to at least one of the first word lines of the first sub-block using a first program method, wherein the first program method is configured to program each of the first memory cells to have a first number of bits;
performing a first erase operation on the first sub-block;
detecting a state of distribution of threshold voltages of second memory cells connected to at least one of the second word lines of the second sub-block;
determining whether a second program operation is to be performed on adjacent second memory cells among the second memory cells using a second program method based on the detected state of distribution of threshold voltages, wherein the adjacent second memory cells are connected to adjacent second word lines among the second word lines including at least one second word line adjacent to the first sub-block; and
programming the adjacent second memory cells connected to the adjacent second word lines using the second program method in response to determining that the second program operation is to be performed, wherein
the second program method is configured to program each of the adjacent second memory cells connected to the adjacent second word lines to have a second number of bits.
2. The method of claim 1 , wherein the first number of bits is more than the second number of bits.
3. The method of claim 1 , further comprising performing a third program operation on adjacent first memory cells among the first memory cells using the second program method, wherein the adjacent first memory cells are connected to adjacent first word lines among the first word lines including at least one first word line adjacent to the second sub-block.
4. The method of claim 1 , further comprising performing a second erase operation on the second sub-block after determining whether the second program operation is to be performed on the adjacent second memory cells and before programming the adjacent second memory cells.
5. The method of claim 1 , wherein the determining of whether the second program operation is to be performed on the adjacent second memory cells comprises:
applying a detection voltage to the adjacent second memory cells and detecting off-cells having threshold voltages that are higher than the detection voltage from among the adjacent second memory cells; and
setting the second program operation to be performed on the adjacent second memory cells by using the second program method when a number of detected off-cells is less than a reference value.
6. The method of claim 1 , wherein the second sub-block further comprises a dummy word line connected to a plurality of memory cells, and at least a portion of the memory cells connected to the dummy word line are programmed only when the adjacent second memory cells connected to the adjacent second word lines are programmed using the second program method.
7. The method of claim 1 , wherein:
the first number of bits is equal to the second number of bits, and
the second program method includes boosting threshold voltages of the adjacent second memory cells to be higher than threshold voltages of the first memory cells achieved by the first program method.
8. The method of claim 7 , wherein the second program method includes applying a program voltage having a higher voltage level than in the first program method to at least one of the adjacent second memory cells during the second program operation.
9. The method of claim 7 , wherein each of the first program method and the second program method is an incremental step pulse (ISPP) method by which a program voltage is gradually increased by as much as a predetermined step voltage.
10. The method of claim 9 , wherein in the second program method, at least one of the step voltage and a pulse application time is greater than in the first program method.
11. The method of claim 1 , wherein:
the first number of bits is equal to the second number of bits, and
the second program method is any one of a method of programming data after an error correction code (ECC) operation by setting a unit of ECC data to be larger than in the first program method, and a method of programming data after an ECC encoding operation is performed a greater number of times than in the first program method.