Shift register unit, gate driving circuit and display device
There are provided a shift register unit, a gate driving circuit and a display device, which enable gate lines in non-output rows to remain in the state of no signal outputting. The shift register unit comprises an input module ( 10 ), a pull-up module ( 20 ), a pull-down control module ( 30 ), a first pull-down module ( 31 ), a second pull-down module ( 40 ) and a reset module ( 50 ). In the non-output time, the first pull-down module and the second pull-down module pull down the output voltages of the pull-up modules connected thereto to a low level alternately, thereby enabling gate lines in non-output rows to remain in the state of no signal outputting.
1. A shift register unit comprising:
an input subcircuit connected to a first signal input terminal and a pull-up control node respectively, and configured to control potential of the pull-up control node according to a signal input by the first signal input terminal;
a pull-up subcircuit connected to a first clock signal terminal, the pull-up control node and a signal output terminal of the present stage respectively, and configured to make the signal output terminal of the present stage output a signal of the first clock signal terminal under the control of the pull-up control node;
a pull-down control subcircuit connected to a voltage terminal, the pull-up control node, the first clock signal terminal, and a pull-down control node respectively, and configured to control the level of the pull-down control node according to the signal input by the first clock signal terminal and the level of the pull-up control node;
a first pull-down subcircuit connected to the voltage terminal, the pull-up control node, the pull-down control node and the signal output terminal of the present stage respectively, and configured to pull down a signal output by the signal output terminal of the present stage to a low level under the control of the pull-down control node;
a second pull-down subcircuit connected to the voltage terminal, a second clock signal terminal and the signal output terminal of the present stage respectively, and configured to pull down the signal output by the signal output terminal of the present stage to a low level according to a signal input by the second clock signal terminal; and
a reset subcircuit connected to the voltage terminal, a second signal input terminal, the pull-up control node and the signal output terminal of the present stage respectively, and configured to reset the potential of the pull-up control node and the signal output by the signal output terminal of the present stage according to a signal input by the second signal input terminal,
wherein the pull-down control subcircuit comprises:
a fourth transistor whose first electrode and gate are connected to the first clock signal terminal;
a fifth transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the second electrode of the fourth transistor and second electrode is connected to the pull-down control node;
a sixth transistor whose first electrode is connected to the reset subcircuit, gate is connected to the pull-down control node and second electrode is connected to the voltage terminal;
a ninth transistor whose first electrode is connected to the second electrode of the fourth transistor, gate is directly connected to the pull-up control node and second electrode is connected to the voltage terminal; and
a tenth transistor whose first electrode is connected to the pull-down control node, gate is connected to the pull-up control node and second electrode is connected to the voltage terminal,
wherein the first pull-down subcircuit comprises:
a seventh transistor whose first electrode is connected to the pull-up control node, gate is connected to the pull-down control node and second electrode is connected to the voltage terminal; and
an eighth transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the pull-down control node and second electrode is connected to the voltage terminal.
2. The shift register unit according to claim 1 , wherein the input subcircuit comprises:
a first transistor whose first electrode and gate are connected to the first signal input terminal and second electrode is connected to the pull-up control node;
a second transistor whose first electrode is connected to the first signal input terminal, gate is connected to the second clock signal terminal and second electrode is connected to the pull-up control node.
3. The shift register unit according to claim 2 , wherein the pull-up subcircuit comprises:
a third transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the pull-up control node and second electrode is connected to the signal output terminal of the present stage; and
a capacitor connected between the gate and the second electrode of the third transistor in parallel.
4. The shift register unit according to claim 1 , wherein the second pull-down subcircuit comprises:
an eleventh transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the second clock signal terminal and second electrode is connected to the voltage terminal.
5. The shift register unit according to claim 4 , wherein the reset subcircuit comprises:
a twelfth transistor whose first electrode is connected to the pull-up control node, gate is connected to the second signal input terminal and second electrode is connected to the voltage terminal;
a thirteenth transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the second signal input terminal and second electrode is connected to the voltage terminal; and
a fourteenth transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the pull-up control node and second electrode is connected to the first electrode of the sixth transistor.
6. The shift register unit according to claim 5 , wherein the reset subcircuit further comprises:
a signal trigger terminal of the next stage connected to the second electrode of the fourteenth transistor.
7. A gate driving circuit comprising multiple stages of shift register units according to claim 1 ;
a signal input terminal of each shift register unit except for the first stage of shift register unit is connected to the signal output terminal of the present stage of its adjacent previous stage of shift register unit; and
a signal output terminal of the present stage of each shift register except for the last stage of shift register unit is connected to the signal input terminal of its adjacent next stage of shift register unit.
8. The gate driving circuit according to claim 7 , wherein
the signal input terminal of each shift register unit except for the first stage of shift register unit is connected to the signal trigger terminal of the next stage of its adjacent previous stage of shift register unit;
the signal trigger terminal of the next stage of each shift register unit except for the last stage of shift register unit is connected to the signal input terminal of its adjacent next stage of shift register unit.
9. The gate driving circuit according to claim 7 , wherein the reset subcircuit comprises:
a twelfth transistor whose first electrode is connected to the pull-up control node, gate is connected to the second signal input terminal and second electrode is connected to the voltage terminal;
a thirteenth transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the second signal input terminal and second electrode is connected to the voltage terminal; and
a fourteenth transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the pull-up control node and second electrode is connected to a first electrode of the sixth transistor.
10. The gate driving circuit according to claim 9 , wherein the reset subcircuit further comprises:
a signal trigger terminal of the next stage connected to the second electrode of the fourteenth transistor.
11. A display device comprising a gate driving circuit according to claim 7 .
12. The gate driving circuit according to claim 7 , wherein the pull-up subcircuit comprises:
a third transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the pull-up control node and second electrode is connected to the signal output terminal of the present stage; and
a capacitor connected between the gate and the second electrode of the third transistor in parallel.
13. The gate driving circuit according to claim 12 , wherein the pull-down control subcircuit comprises:
a fourth transistor whose first electrode and gate are connected to the first clock signal terminal;
a fifth transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the second electrode of the fourth transistor and second electrode is connected to the pull-down control node;
a sixth transistor whose first electrode is connected to the reset subcircuit, gate is connected to the pull-down control node and second electrode is connected to the voltage terminal;
a ninth transistor whose first electrode is connected to the second electrode of the fourth transistor, gate is connected to the pull-up control node and second electrode is connected to the voltage terminal; and
a tenth transistor whose first electrode is connected to the pull-down control node, gate is connected to the pull-up control node and second electrode is connected to the voltage terminal.
14. The gate driving circuit according to claim 13 , wherein the first pull-down subcircuit comprises:
a seventh transistor whose first electrode is connected to the pull-up control node, gate is connected to the pull-down control node and second electrode is connected to the voltage terminal; and
an eighth transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the pull-down control node and second electrode is connected to the voltage terminal.
15. The gate driving circuit according to claim 14 , wherein the second pull-down subcircuit comprises:
an eleventh transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the second clock signal terminal and second electrode is connected to the voltage terminal.
16. The gate driving circuit according to claim 15 , wherein the reset subcircuit comprises:
a twelfth transistor whose first electrode is connected to the pull-up control node, gate is connected to the second signal input terminal and second electrode is connected to the voltage terminal;
a thirteenth transistor whose first electrode is connected to the signal output terminal of the present stage, gate is connected to the second signal input terminal and second electrode is connected to the voltage terminal; and
a fourteenth transistor whose first electrode is connected to the first clock signal terminal, gate is connected to the pull-up control node and second electrode is connected to the first electrode of the sixth transistor.
17. The gate driving circuit according to claim 16 , wherein the reset subcircuit further comprises:
a signal trigger terminal of the next stage connected to the second electrode of the fourteenth transistor.
18. The gate driving circuit according to claim 17 , wherein the reset subcircuit further comprises:
a signal trigger terminal of the next stage connected to the second electrode of the fourteenth transistor.
19. The gate driving circuit according to claim 7 , wherein the input subcircuit comprises:
a first transistor whose first electrode and gate are connected to the first signal input terminal and second electrode is connected to the pull-up control node;
a second transistor whose first electrode is connected to the first signal input terminal, gate is connected to the second clock signal terminal and second electrode is connected to the pull-up control node.