Temperature compensated read assist circuit for a static random access memory (SRAM)
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.
1. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a pull-down transistor having a source-drain path connected between the wordline and a ground node; and
a bias circuit configured to apply a temperature dependent biasing voltage to a control terminal of the pull-down transistor;
wherein the bias circuit comprises:
a first diode-connected transistor coupled between a positive supply voltage node and the control terminal of the pull-down transistor; and
a second diode-connected transistor coupled between the control terminal of the pull-down transistor and the ground node.
2. The circuit of claim 1 , further comprising a wordline driver circuit including a p-channel pull-up transistor, said pull-down transistor being an n-channel transistor.
3. The circuit of claim 1 , wherein the first diode-connected transistor is an n-channel transistor and the second diode-connected transistor is a p-channel transistor.
4. The circuit of claim 1 , wherein the first diode-connected transistor is an n-channel transistor.
5. The circuit of claim 1 , wherein the temperature dependent biasing voltage varies as a function of temperature dependent change in a threshold voltage of the first diode-connected transistor.
6. The circuit of claim 1 , wherein the temperature dependent biasing voltage is relatively lower for lower temperatures and relatively higher for higher temperatures.
7. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a pull-down transistor having a source-drain path connected between the wordline and a ground node; and
a bias circuit configured to apply a temperature dependent biasing voltage to a control terminal of the pull-down transistor, said bias circuit include a clamp circuit operating to clamp a minimum value of the temperature dependent biasing voltage to a voltage level higher than a voltage at the ground node.
8. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a wordline driver circuit including a p-channel pull-up transistor;
an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node; and
an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor, said n-channel diode-connected transistor configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.
9. The circuit of claim 8 , further comprising a p-channel diode-connected transistor coupled between the control terminal of the pull-down transistor and the ground node and functioning to clamp a minimum voltage at the gate terminal of the n-channel pull-down transistor.
10. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a pull-down transistor having a source-drain path connected between the wordline and a ground node;
a bias circuit configured to apply a temperature dependent biasing voltage to a control terminal of the pull-down transistor; and
a clamping circuit configured to clamp a minimum value of the temperature dependent biasing voltage to a value that is at least a transistor threshold voltage above a voltage at the ground node.
11. The circuit of claim 10 , further comprising a wordline driver circuit including a p-channel pull-up transistor, said pull-down transistor being an n-channel transistor.
12. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a wordline driver circuit including a p-channel pull-up transistor, said pull-down transistor being an n-channel transistor;
a pull-down transistor having a source-drain path connected between the wordline and a ground node; and
a bias circuit configured to apply a temperature dependent biasing voltage to a control terminal of the pull-down transistor, wherein a minimum value of the temperature dependent biasing voltage is clamped;
wherein the bias circuit comprises a first diode-connected transistor coupled between a positive supply voltage node and the control terminal of the pull-down transistor.
13. The circuit of claim 12 , wherein the bias circuit further comprises a second diode-connected transistor coupled between the control terminal of the pull-down transistor and the ground node.
14. The circuit of claim 13 , wherein the first diode-connected transistor is an n-channel transistor and the second diode-connected transistor is a p-channel transistor.
15. The circuit of claim 12 , wherein the first diode-connected transistor is an n-channel transistor.
16. The circuit of claim 12 , wherein the temperature dependent biasing voltage varies as a function of temperature dependent change in a threshold voltage of the first diode-connected transistor.
17. The circuit of claim 10 , wherein the temperature dependent biasing voltage is relatively lower for lower temperatures and relatively higher for higher temperatures.
18. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a pull-down transistor having a drain terminal directly connected to the wordline and a source terminal coupled to a ground node; and
a bias circuit configured to apply a temperature dependent biasing voltage to a control terminal of the pull-down transistor;
wherein the bias circuit comprises a first diode-connected transistor coupled between a positive supply voltage node and the control terminal of the pull-down transistor; and
wherein the first diode-connected transistor is an n-channel transistor.
19. The circuit of claim 18 , further comprising a wordline driver circuit including a p-channel pull-up transistor, said pull-down transistor being an n-channel transistor.
20. The circuit of claim 19 , wherein the bias circuit further comprises a second diode-connected transistor coupled between the control terminal of the pull-down transistor and the ground node.
21. The circuit of claim 20 , wherein the first diode-connected transistor is an n-channel transistor and the second diode-connected transistor is a p-channel transistor.
22. The circuit of claim 18 , wherein a minimum value of the temperature dependent biasing voltage is clamped.