Semiconductor integrated circuit

1. A semiconductor integrated circuit, comprising:

a substrate;

a first transistor and a second transistor each having a source region, a drain region in the substrate and a gate region on the substrate;

a first patterned conductive layer, over the first and second transistors, having a first portion and a second portion, the first portion of the first patterned conductive layer being electrically connected to the drain region of the first transistor, the second portion of the first patterned conductive layer being electrically connected to the drain region of the second transistor, the first and second portions of the first patterned conductive layer being isolated from each other;

a second patterned conductive layer over the first patterned conductive layer;

a storage element between the first portion of the first patterned conductive layer and the second patterned conductive layer; and

a first conductive element directly connected from the second portion of the first patterned conductive layer to the second patterned conductive layer;

wherein the second portion of the first patterned conductive layer further comprises a first section and a second section, and the first section is electrically isolated from the second section and the drain region of the second transistor.

2. The semiconductor integrated circuit of claim 1 further comprising a third transistor having a source region, a drain region in the substrate and a gate region on the substrate, wherein first patterned conductive layer on the third transistor further comprises a third portion electrically connected to the drain region of the third transistor, wherein the first, second and third portions of the first patterned conductive layer are isolated from one another.

3. The semiconductor integrated circuit of claim 2 , wherein the whole third portion of the first patterned conductive layer is isolated from the second patterned conductive layer.

4. The semiconductor integrated circuit of claim 2 , wherein at least a portion of the third portion of the first patterned conductive layer is isolated from the second patterned conductive layer.

5. The semiconductor integrated circuit of claim 4 , wherein the third portion of the first patterned conductive layer and/or the second patterned conductive layer further comprises a fusible device.

6. The semiconductor integrated circuit of claim 1 , further comprising a third transistor having a source region, a drain region in the substrate and a gate region on the substrate, wherein the first patterned conductive layer is disposed over the third transistor and further comprises a third portion, wherein the first, second and third portions of the first patterned conductive layer are isolated from one another and the third portion of the first patterned conductive layer comprises a first section and a second section isolated from the first section.

7. The semiconductor integrated circuit of claim 6 further comprising a second conductive element, the second conductive element electrically connects the first section of the third portion of the first patterned conductive layer to the second patterned conductive layer.

8. The semiconductor integrated circuit of claim 6 , wherein the second section of the third portion of the first patterned conductive layer is electrically connected to the drain region of the third transistor.

9. The semiconductor integrated circuit of claim 1 , wherein the first conductive element is a fusible device.

10. The semiconductor integrated circuit of claim 1 , wherein the second portion of the first patterned conductive layer further comprises a fusible device.

11. The semiconductor integrated circuit of claim 10 , wherein the fusible device divides the second portion of the first patterned conductive layer into the first section and the second section.

12. A semiconductor integrated circuit, comprising:

a substrate;

a first transistor and a second transistor each having a source region, a drain region in the substrate and a gate region on the substrate;

a first patterned conductive layer, over the first and second transistors, having at least a first portion and a second portion, the first portion of the first patterned conductive layer being electrically connected to the drain region of the first transistor, the second portion of the first patterned conductive layer being electrically connected to the drain region of the second transistor, the first and second portions of the first patterned conductive layer being isolated from each other;

a second patterned conductive layer over the first patterned conductive layer; and

a storage element between the first portion of the first patterned conductive layer and the second patterned conductive layer,

wherein the second portion of the first patterned conductive layer comprises a first section and a second section isolated from the first section, and the first section and the second section are formed on a same layer on the substrate.

13. The semiconductor integrated circuit of claim 12 , wherein the whole second portion of the first patterned conductive layer is isolated from the second patterned conductive layer.

14. The semiconductor integrated circuit of claim 12 , wherein the second portion of the first patterned conductive layer and/or the second patterned conductive layer further comprises a fusible device.

15. The semiconductor integrated circuit of claim 12 further comprising a conductive element, the conductive element electrically connects the first section of the second portion of the first patterned conductive layer to the second patterned conductive layer.

16. A semiconductor integrated circuit, comprising:

a substrate;

a first transistor and a second transistor each having a source region, a drain region in the substrate and a gate region on the substrate;

a first patterned conductive layer having a first portion and a second portion, the first portion electrically connected to the drain region of the first transistor, and the first portion comprising a first section, a second section and a fusible device, and the second portion electrically connected to the drain region of the second transistor;

wherein the first section, the second section and the fusible device are formed on a same height measured from the substrate.

17. The semiconductor integrated circuit of claim 16 , wherein the fusible device is disposed between the first section and the second section.

18. The semiconductor integrated circuit of claim 16 further comprising a conductive element and a second patterned conductive layer over the first patterned conductive layer, wherein the conductive element electrically connects the first section of the first patterned conductive layer to the second patterned conductive layer.