Semiconductor light emitting device

1. A semiconductor light emitting device, comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type;

a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer;

a first transistor including a first gate electrode and a first amorphous semiconductor layer, the first gate electrode and the first amorphous semiconductor layer overlapping in a first direction, the first direction being from the first semiconductor layer toward the second semiconductor layer;

a first layer;

a first electrode; and

a second electrode,

the first gate electrode being provided between the second semiconductor layer and the first amorphous semiconductor layer,

the first semiconductor layer further including a first region and a second region, the second region being arranged with the first region in a second direction intersecting the first direction,

the second semiconductor layer being provided between the second region and the first layer,

the third semiconductor layer being provided between the second region and the second semiconductor layer,

the first electrode being provided between the first region and the first layer and electrically connected to the first region,

the second electrode being provided between the second semiconductor layer and the first layer and electrically connected to the second semiconductor layer.

2. The device according to claim 1 , wherein

the first region is disposed around the second region when projected onto a plane perpendicular to the first direction, and

the first electrode and a portion of the first region overlap in the first direction.

3. The device according to claim 1 , wherein

the first amorphous semiconductor layer further includes a third region, a fourth region, and a fifth region, one end of the first transistor being provided at the third region, the fourth region being arranged with the third region in the second direction, one other end of the first transistor being provided at the fourth region, the fifth region being provided between the third region and the fourth region, the first gate electrode and the fifth region overlapping in the first direction,

the first layer is conductive and electrically connected to the third region, and

the first electrode is electrically connected to the fourth region.

4. The device according to claim 1 , further comprising:

a region provided between the first electrode and the second electrode in the second direction; and

an interconnect provided between the first electrode and the first layer in the first direction,

the interconnect and the region overlapping in the first direction.

5. The device according to claim 1 , further comprising:

a second transistor; and

a third transistor,

the first amorphous semiconductor layer further including a third region, a fourth region, and a fifth region, one end of the first transistor being provided at the third region, the fourth region being arranged with the third region in the second direction, one other end of the first transistor being provided at the fourth region, the fifth region being provided between the third region and the fourth region, the first gate electrode and the fifth region overlapping in the first direction,

the first gate electrode being electrically connected to the second transistor,

the third region being electrically connected to the second electrode,

the fourth region being electrically connected to the third transistor.

6. The device according to claim 1 , further comprising:

a fourth transistor;

a fourth semiconductor layer of the second conductivity type; and

a fifth semiconductor layer provided between the first semiconductor layer and the fourth semiconductor layer,

the fourth transistor including

a second gate electrode, and

a second amorphous semiconductor layer, the second gate electrode and the second amorphous semiconductor layer overlapping in the first direction,

the second gate electrode being provided between the fourth semiconductor layer and the second amorphous semiconductor layer.

7. The device according to claim 1 , further comprising:

a fourth transistor;

a sixth semiconductor layer of the first conductivity type, the sixth semiconductor layer being separated from the first semiconductor layer;

a seventh semiconductor layer of the second conductivity type; and

an eighth semiconductor layer provided between the sixth semiconductor layer and the seventh semiconductor layer,

the fourth transistor including

a second gate electrode, and

a second amorphous semiconductor layer, the second gate electrode and the second amorphous semiconductor layer overlapping in the first direction,

the second gate electrode being provided between the seventh semiconductor layer and the second amorphous semiconductor layer in the first direction.

8. The device according to claim 1 , wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer each include a nitride semiconductor.

9. The device according to claim 1 , wherein the first electrode includes aluminum, nickel, and gold.

10. The device according to claim 1 , wherein the second electrode includes silver and platinum.

11. The device according to claim 1 , wherein the first amorphous semiconductor layer includes an oxide of at least one of indium, gallium, or zinc.

12. The device according to claim 1 , wherein a hydrogen atom concentration of the first amorphous semiconductor layer is not less than 10 18 atoms/cm 3 and not more than 10 22 atoms/cm 3 .

13. The device according to claim 1 , wherein the first semiconductor layer further has a major surface provided on a side opposite to the third semiconductor layer, a plurality of protrusions being provided in the major surface.

14. A semiconductor light emitting device, comprising:

a first semiconductor layer of a first conductivity type:

a second semiconductor layer of a second conductivity type;

a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer;

a first transistor including a first gate electrode and a first amorphous semiconductor layer, the first gate electrode and the first amorphous semiconductor layer overlapping in a first direction, the first direction being from the first semiconductor layer toward the second semiconductor layer; and

a second transistor,

the second transistor being electrically connected to the first gate electrode.

15. The device according to claim 14 , wherein

a first region is disposed around a second region when projected onto a plane perpendicular to the first direction, and

a first electrode and a portion of the first region overlap in the first direction.

16. The device according to claim 14 , wherein

the first amorphous semiconductor layer further includes a third region, a fourth region, and a fifth region, one end of the first transistor being provided at the third region, the fourth region being arranged with the third region in the second direction, one other end of the first transistor being provided at the fourth region, the fifth region being provided between the third region and the fourth region, the first gate electrode and the fifth region overlapping in the first direction,

a first layer,

the first layer is conductive and electrically connected to the third region, and

the first electrode is electrically connected to the fourth region.

17. The device according to claim 14 , further comprising:

a region provided between a first electrode and a second electrode in the second direction; and

an interconnect provided between the first electrode and a first layer in the first direction,

the interconnect and a region overlapping in the first direction.

18. The device according to claim 14 , further comprising:

a third transistor,

the first amorphous semiconductor layer further including a third region, a fourth region, and a fifth region, one end of the first transistor being provided at the third region, the fourth region being arranged with the third region in the second direction, one other end of the first transistor being provided at the fourth region, the fifth region being provided between the third region and the fourth region, the first gate electrode and the fifth region overlapping in the first direction,

the first gate electrode being electrically connected to the second transistor,

the third region being electrically connected to a second electrode, and

the fourth region being electrically connected to the third transistor.

19. The device according to claim 14 , further comprising:

a fourth transistor;

a fourth semiconductor layer of the second conductivity type; and

a fifth semiconductor layer provided between the first semiconductor layer and the fourth semiconductor layer,

the fourth transistor including

a second gate electrode, and

a second amorphous semiconductor layer, the second gate electrode and the second amorphous semiconductor layer overlapping in the first direction,

the second gate electrode being provided between the fourth semiconductor layer and the second amorphous semiconductor layer.

20. The device according to claim 14 , further comprising:

a fourth transistor:

a sixth semiconductor layer of the first conductivity type, the sixth semiconductor layer being separated from the first semiconductor layer;

a seventh semiconductor layer of the second conductivity type; and

an eighth semiconductor layer provided between the sixth semiconductor layer and the seventh semiconductor layer,

the fourth transistor including

a second gate electrode, and

a second amorphous semiconductor layer, the second gate electrode and the second amorphous semiconductor layer overlapping in the first direction,

the second gate electrode being provided between the seventh semiconductor layer and the second amorphous semiconductor layer in the first direction.