Semiconductor device, manufacturing method thereof, and electronic device
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).
1. A semiconductor device comprising:
a first insulating layer over a substrate;
a first metal oxide layer over the first insulating layer;
an oxide semiconductor layer over the first metal oxide layer;
a second metal oxide layer over the oxide semiconductor layer;
a gate insulating layer over the second metal oxide layer; and
a gate electrode layer over the gate insulating layer,
wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the first region and the second region each comprise a region overlapping with the gate electrode layer,
wherein the second region is between the first region and the third region,
wherein the second region comprises a region with lower resistance than the first region,
wherein the third region comprises a region with lower resistance than the second region,
wherein the second region and the third region each comprise a region containing an element N, and
wherein N is phosphorus, argon, or xenon.
2. A semiconductor device comprising:
a first insulating layer over a substrate;
a first metal oxide layer over the first insulating layer;
an oxide semiconductor layer over the first metal oxide layer;
a second metal oxide layer over the first insulating layer and the oxide semiconductor layer;
a first gate insulating layer over the second metal oxide layer; and
a gate electrode layer over the first gate insulating layer,
wherein the second metal oxide layer and the first gate insulating layer each comprise a region facing side surfaces of the first metal oxide layer and the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the first region and the second region each comprise a region overlapping with the gate electrode layer,
wherein the second region is between the first region and the third region,
wherein the second region comprises a region with lower resistance than the first region,
wherein the third region comprises a region with lower resistance than the second region,
wherein the second region and the third region each comprise a region containing an element N, and
wherein N is phosphorus, argon, or xenon.
3. The semiconductor device according to claim 2 , wherein a second gate insulating layer is between the first gate insulating layer and the gate electrode layer.
4. The semiconductor device according to claim 1 , wherein the second region comprises a region containing the element N at a higher concentration than that in the first region, and the third region comprises a region containing the element N at a higher concentration than that in the second region.
5. The semiconductor device according to claim 1 , wherein the third region comprises a region containing the element N at a concentration higher than or equal to 1×10 18 atoms/cm 3 and lower than or equal to 1×10 22 atoms/cm 3 .
6. A semiconductor device comprising:
a first insulating layer over a substrate;
a first metal oxide layer over the first insulating layer;
an oxide semiconductor layer over the first metal oxide layer;
a second metal oxide layer over the oxide semiconductor layer;
a gate insulating layer over the second metal oxide layer;
a second insulating layer over the second metal oxide layer; and
a gate electrode layer over the gate insulating layer,
wherein the gate insulating layer comprises a region in contact with a side surface of the gate electrode layer,
wherein the second insulating layer comprises a region in contact with the gate insulating layer,
wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the first region comprises a region overlapping with the gate electrode layer,
wherein the second region comprises a region overlapping with the gate insulating layer or the second insulating layer,
wherein the second region is between the first region and the third region,
wherein the second region and the third region each comprise a region containing an element N, and
wherein N is phosphorus, argon, or xenon.
7. The semiconductor device according to claim 6 , wherein the second region comprises a region with lower resistance than the first region, and the third region comprises a region with lower resistance than the second region.
8. The semiconductor device according to claim 6 further comprising a region where an angle between a bottom surface of the substrate and a tangent of a side surface of the gate electrode layer is greater than or equal to 60° and less than or equal to 85°.
9. An electronic device comprising:
the semiconductor device according to claim 1 ;
a housing; and
a speaker.