Methods, apparatus, instructions and logic to provide vector packed histogram functionality
Instructions and logic provide SIMD vector packed histogram functionality. Some processor embodiments include first and second registers storing, in each of a plurality of data fields of a register lane portion, corresponding elements of a first and of a second data type, respectively. A decode stage decodes an instruction for SIMD vector packed histograms. One or more execution units, compare each element of the first data type, in the first register lane portion, with a range specified by the instruction. For any elements of the first register portion in said range, corresponding elements of the second data type, from the second register portion, are added into one of a plurality data fields of a destination register lane portion, selected according to the value of its corresponding element of the first data type, to generate packed weighted histograms for each destination register lane portion.
1. A method comprising:
storing in each of a plurality of p data fields of a first vector register portion, an element of a first data type;
storing in each of a plurality of p data fields of a second vector register or memory vector portion, a corresponding element of a second data type;
executing, in a processor, a instruction for vector packed histogram; by comparing each element of the first data type, in said plurality of p data fields of the first vector register portion, with a range specified by the instruction; and
for any elements of the first vector register portion in said range, adding a corresponding element of the second data type, from the second vector register or memory vector portion, into one of a plurality of q data fields, of a destination vector register portion, selected according to a value of the corresponding element of the first data type.
2. The method of claim 1 , wherein the first data type is a 16-bit integer.
3. The method of claim 1 , wherein the second data type is a 16-bit integer.
4. The method of claim 1 , wherein the second data type is a 16-bit floating-point number.
5. The method of claim 1 , wherein said plurality of p data fields has four data fields.
6. The method of claim 1 , wherein said plurality of p data fields has eight data fields.
7. The method of claim 1 , wherein said plurality of p data fields has sixteen data fields.
8. The method of claim 1 , wherein said plurality of p data fields consists of the same number of data fields as in said plurality of q data fields.
9. The method of claim 1 , wherein each of said plurality of p data fields consists of the same number of bits as each of said plurality of q data fields.
10. The method of claim 1 , wherein each of said plurality of p data fields consists of at least half as many bits as each of said plurality of q data fields.
11. The method of claim 1 , wherein said plurality of q data fields has four data fields.
12. The method of claim 1 , wherein said plurality of q data fields has eight data fields.
13. The method of claim 1 , wherein said plurality of q data fields comprises at least nine data fields.
14. A processing system comprising:
a memory; and
a plurality of processors each processor comprising:
a first register storing in each of a plurality of p data fields of a first register portion, an element of a first data type;
a second register or memory storage set storing in each of a plurality of p data fields of a second register or memory storage set portion, a corresponding element of a second data type;
a decode stage to decode a instruction for vector packed histogram; and
one or more execution units, responsive to the decoded instruction, to:
compare each element of the first data type, in said plurality of p data fields of the first register portion, with a range specified by the instruction; and
for any elements of the first register portion in said range, add a corresponding element of the second data type, from said plurality of p data fields of the
second register or memory storage set portion, into one of a plurality of q data fields, of a destination register portion, selected according to a value of its corresponding element of the first data type.
15. The processing system of claim 14 , wherein each of said plurality of p data fields consists of the same number of bits as each of said plurality of q data fields.
16. The processing system of claim 14 , wherein each of said plurality of p data fields consists of at least half as many bits as each of said plurality of q data fields.
17. The processing system of claim 14 , wherein said plurality of p data fields has four data fields.
18. The processing system of claim 14 , wherein said plurality of p data fields has eight data fields.
19. The processing system of claim 14 , wherein said plurality of p data fields has sixteen data fields.
20. The processing system of claim 14 , wherein the first data type is an 8-bit integer.
21. The processing system of claim 14 , wherein the second data type is a 16-bit integer.
22. The processing system of claim 14 , wherein the second data type is a 16-bit floating-point number.
23. The processing system of claim 14 , wherein the range is specified by the instruction in an immediate operand.
24. The processing system of claim 14 , wherein the range is specified in an operation code of the instruction.
25. The processing system of claim 14 , wherein the range is specified as one of a set of initial values in the plurality of q data fields of said destination register portion.