IP Library Granted Patent US 9,876,046
Granted Patent B2
US 9,876,046 · App. 15/073,611 · Granted Jan 23, 2018

Imaging device comprising multilayer wiring structure and capacitance element capable of having relatively larger capacitance value

Inventors: Yuuko Tomekawa (Osaka, JP); Tokuhiko Tamaki (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L27/14643H01L27/14603H01L27/14609H01L27/14612H01L27/14623H01L27/14636H01L27/14665H04N5/363H01L27/307H04N5/23245
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Quick Facts
Patent No.
US 9,876,046
App. No.
15/073,611
Granted
Jan 23, 2018
Kind
B2
Abstract

An imaging device includes: a semiconductor substrate; a photoelectric conversion element including a first electrode, a second electrode, and a photoelectric conversion film, supported on the semiconductor substrate, and generating a signal by performing photoelectric conversion on incident light; a multilayer wiring structure including an upper wiring layer and a lower wiring layer provided between the semiconductor substrate and the second electrode; and a signal detection circuit provided in the semiconductor substrate and the multilayer wiring structure, including a signal detection transistor and a first capacitance element, and detecting the signal. The signal detection transistor includes a gate and a source region and a drain region, the first capacitance element includes a first lower electrode, a first upper electrode, and a dielectric film disposed therebetween, the upper wiring layer is disposed between the second electrode and the gate, and the upper wiring layer includes the first upper electrode.

Claims (40)

1. An imaging device comprising:

a semiconductor substrate;

a photoelectric conversion element that includes a first electrode, a second electrode, and a photoelectric conversion film between the first electrode and the second electrode, is supported on the semiconductor substrate, and, in operation, generates a signal by performing photoelectric conversion on incident light;

a multilayer wiring structure including an upper wiring layer and a lower wiring layer which are provided between the semiconductor substrate and the second electrode of the photoelectric conversion element; and

a signal detection circuit that is provided in the semiconductor substrate and the multilayer wiring structure, includes a signal detection transistor and a first capacitance element, and, in operation, detects the signal, wherein

the signal detection transistor includes a gate, and a source region and a drain region which are provided in the semiconductor substrate,

the first capacitance element includes a first lower electrode, a first upper electrode, and a dielectric film disposed between the first upper electrode and the first lower electrode,

the upper wiring layer is disposed between the second electrode of the photoelectric conversion element and the gate of the signal detection transistor, and

the upper wiring layer includes the first upper electrode.

2. The imaging device according to claim 1 , wherein

the lower wiring layer is disposed between the upper wiring layer and the gate of the signal detection transistor, and

the lower wiring layer includes the first lower electrode.

3. The imaging device according to claim 1 , wherein

the signal detection circuit further includes a second capacitance element including a second lower electrode and a second upper electrode,

a capacitance of the second capacitance element is smaller than a capacitance of the first capacitance element, and

one of the second lower electrode and the second upper electrode is connected to one of the first lower electrode and the first upper electrode.

4. The imaging device according to claim 3 , wherein

the other of the second lower electrode and the second upper electrode is connected to the second electrode of the photoelectric conversion element.

5. The imaging device according to claim 1 , further comprising:

a feedback circuit that, in operation, provides negative feedback on an output of the signal detection circuit, wherein

the feedback circuit includes an output line,

the signal detection circuit further includes a reset transistor including a source and a drain,

one of the source and the drain of the reset transistor is connected to the second electrode of the photoelectric conversion element, and

the other of the source and the drain of the reset transistor is connected to the output line.

6. The imaging device according to claim 1 , wherein

the multilayer wiring structure further includes a connector which connects the second electrode of the photoelectric conversion element and the gate of the signal detection transistor, and

one of the first upper electrode and the first lower electrode surrounds the connector when viewed from a normal direction of the semiconductor substrate.

7. The imaging device according to claim 1 , wherein

the multilayer wiring structure further includes a signal line which, in operation, applies a reference voltage to the first upper electrode,

the first upper electrode has a first surface facing the second electrode of the photoelectric conversion element and a second surface on a side opposite to the first surface, and

the first upper electrode is connected to the signal line on the second surface.

8. The imaging device according to claim 1 , wherein

the first upper electrode covers a surface of the dielectric film other than a portion of the surface which faces the first lower electrode.

9. The imaging device according to claim 1 , wherein

the second electrode of the photoelectric conversion element and the first upper electrode are formed of a same material.

10. The imaging device according to claim 1 , further comprising:

a shielding electrode which surrounds the second electrode of the photoelectric conversion element when viewed from a normal direction of the semiconductor substrate,

wherein a space is disposed between the shielding electrode and the second electrode of the photoelectric conversion element.

11. The imaging device according to claim 10 , wherein

when viewed from the normal direction of the semiconductor substrate, the first upper electrode is disposed between the second electrode of the photoelectric conversion element and the shielding electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2016
From: TOMEKAWA, YUUKO; TAMAKI, TOKUHIKO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 038211/0233 →
Priority Claims (1)
JP 2015-075729 · Apr 2, 2015 · national
Continuity (1)
Related Publication 20160293654A1 · Oct 6, 2016