Trench power transistor structure and manufacturing method thereof
A trench power transistor and a manufacturing method thereof are provided. The trench power transistor includes a substrate, an epitaxial layer, a trench gate structure, a body region, and a source region. The epitaxial layer disposed on the substrate has a trench formed therein. The trench gate structure disposed in the trench includes a bottom dielectric structure, a gate dielectric layer, and a gate. The bottom dielectric structure formed in a lower portion of the trench includes an insulating layer formed along a first inner wall of the lower portion of the trench defining a groove, and a non-conductive structure formed in the groove. The gate dielectric layer is formed along a second inner wall of an upper portion of the trench, and the gate is formed in the trench and connects the gate dielectric layer. The body region and the source region are formed in the epitaxial layer.
1. A trench power transistor comprising :
a substrate;
an epitaxial layer formed on the substrate, wherein the epitaxial layer has a trench formed therein;
a trench gate structure disposed in the trench and comprising:
a bottom dielectric structure formed in a lower portion of the trench, wherein the bottom dielectric structure includes an insulating layer and a non-conductive structure, the insulating layer is formed along a first inner wall of the lower portion of the trench defining a groove, and the non-conductive structure is made of intrinsic semiconductor and formed in the groove;
a gate dielectric layer formed along a second inner wall of an upper portion of the trench; and
a gate formed in the trench and connecting the gate dielectric layer;
a body region formed in the epitaxial layer and surrounding the trench gate structure; and
a source region formed in the epitaxial layer and located over the body region.
2. The trench power transistor according to claim 1 , wherein a top face of the non-conductive structure is located at a higher level than a top surface of the insulating layer.
3. The trench power transistor according to claim 1 , wherein the gate dielectric layer completely covers a top surface of the insulating layer.
4. The trench power transistor according to claim 1 , wherein a top surface of the insulating layer is located at a level equal to or lower than a lowest edge of the body region.
5. The trench power transistor according to claim 1 , wherein the gate is a heavily doped polysilicon structure and the non-conductive structure is an un-doped polysilicon structure.
6. The trench power transistor according to claim 5 , wherein a portion of the gate dielectric layer completely covers a top face of the non-conductive structure so that the gate and the non-conductive structure are isolated from each other.
7. The trench power transistor according to claim 1 , wherein a portion of the insulating layer formed on a sidewall surface of the trench has a side thickness, and a ratio of the side thickness to a trench width ranges from 0.2 to 0.5.
8. A manufacturing method of a trench power transistor comprising:
providing a substrate;
forming an epitaxial layer on the substrate;
forming a trench in the epitaxial layer;
forming a bottom dielectric structure in a lower portion of the trench, wherein the bottom dielectric structure includes an insulating layer formed along a first inner wall of the lower portion of the trench defining a groove, and a non-conductive structure made of intrinsic semiconductor and formed in the groove;
forming a gate dielectric layer along a second inner wall of an upper portion of the trench;
forming a gate in the trench;
performing a base doping process in the epitaxial layer to form a body region; and
performing a source implantation to form a source region located over the body region.
9. The manufacturing method of the trench power transistor according to claim 8 , wherein the step of forming the bottom dielectric structure comprising:
forming a first insulating layer to cover an inner wall of the trench, wherein the first insulating layer defines a first groove in the trench;
filling a non-conductive material in the first groove;
removing a portion of the non-conductive material located at the upper portion of the trench to form the non-conductive structure at the lower portion of the trench; and
partially removing the first insulating layer located at the upper portion of the trench to form the insulating layer located at the lower portion of the trench.
10. The manufacturing method of the trench power transistor according to claim 8 , wherein a top face of the non-conductive structure is located at a higher level than a top surface of the insulating layer.
11. The manufacturing method of the trench power transistor according to claim 8 , wherein the trench extends from a top surface of the epitaxial layer to a depth greater than that of the body region. The manufacturing method of the trench power transistor according to claim 8 , wherein a top surface of the insulating layer is located at a level equal to or lower than a lowest edge of the body region.
12. The manufacturing method of the trench power transistor according to claim 8 , wherein a top surface of the insulating layer is located at a level equal to or lower than a lowest edge of the body region.
13. The manufacturing method of the trench power transistor according to claim 8 , wherein the gate is a heavily doped polysilicon structure and the non-conductive structure is an un-doped polysilicon structure.
14. The manufacturing method of the trench power transistor according to claim 13 , wherein a portion of the gate dielectric layer completely covers a top face of the non-conductive structure so that the gate and the non-conductive structure are isolated from each other.
15. The manufacturing method of the trench power transistor according to claim 8 , wherein a portion of the insulating layer formed on a sidewall surface of the trench has a side thickness, and a ratio of the side thickness to a trench width ranges from 0.2 to 0.5.