Structure and method for 3D FinFET metal gate
The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.
1. A semiconductor structure, comprising:
a semiconductor substrate; and
a gate stack disposed on the semiconductor substrate;
wherein the gate stack includes a high k dielectric material layer, and a plurality of metal layers disposed over the high-k dielectric material layer, wherein the gate stack has a convex top surface that includes a topmost surface of each of the plurality of metal layers.
2. The semiconductor structure of claim 1 , wherein the convex top surface of the gate stack has a height difference H and a width W; and a ratio H/W ranges from about 10% to about 50%.
3. The semiconductor structure of claim 2 , wherein the height difference H ranges from about 2 nm to about 10 nm.
4. The semiconductor structure of claim 1 , further comprising a top capping layer disposed over the convex top surface of the gate stack in edge areas such that a portion of the convex top surface extends through the top capping layer.
5. The semiconductor structure of claim 4 , wherein the top capping layer includes a dielectric material selected from the group consisting of silicon oxide, silicon nitride, low-k dielectric material, and a combination thereof.
6. The semiconductor structure of claim 1 , wherein the gate stack includes
an interfacial layer over the semiconductor substrate;
the high-k dielectric material layer over the interfacial layer;
a capping layer over the high-k dielectric material layer;
a work function metal layer disposed over the capping layer;
a blocking layer over the work function metal layer; and
a filling metal layer.
7. The semiconductor structure of claim 6 , further comprising another blocking layer disposed between the work function metal layer and the capping layer.
8. The semiconductor structure of claim 6 , wherein
the interfacial layer includes silicon oxide;
the capping layer includes one of titanium nitride and tantalum nitride;
the blocking layer includes one of titanium nitride and tantalum nitride; and
the filling metal layer includes one of aluminum and tungsten.
9. A semiconductor structure, comprising:
a semiconductor substrate; and
a gate stack disposed over the semiconductor substrate; wherein the gate stack includes
a gate dielectric layer including a high k dielectric material;
a capping layer disposed over the high k dielectric material layer;
a work function metal layer disposed over the capping layer;
a blocking layer disposed over the work function metal layer; and
a filling metal layer disposed over the blocking layer,
wherein the gate stack has a convex top surface including a topmost surface of the filling metal layer and a topmost surface of a gate stack layer from a group consisting of the gate dielectric layer, the capping layer, the work function layer, and the blocking layer.
10. The semiconductor structure of claim 9 , wherein the convex top surface of the gate stack has a height difference H and a width W; and a ratio H/W ranges from about 10% to about 50%.
11. The semiconductor structure of claim 10 , wherein the height difference H ranges from about 2 nm to about 10 nm.
12. The semiconductor structure of claim 9 , further comprising a top capping layer disposed over the convex top surface of the gate stack in edge areas such that a portion of the convex top surface extends through the top capping layer.
13. The semiconductor structure of claim 12 , wherein the top capping layer includes a dielectric material selected from the group consisting of silicon oxide, silicon nitride, low-k dielectric material, and a combination thereof.
14. A method of forming a semiconductor structure, comprising:
forming a dummy gate over a semiconductor substrate;
forming an interlayer dielectric layer over the substrate;
removing the dummy gate, resulting in a gate trench in the interlayer dielectric layer;
forming a plurality of gate material layers to fill in the gate trench, wherein the gate material layers include a gate dielectric layer and a plurality of metal layers, and further include a top surface that includes a first material of a first layer of the plurality of gate material layers and a second material of a second layer of the plurality of gate material layers; and
performing a selective removing process on the top surface wherein the first material of the first layer and the second material of the second layer are removed at different rates, thereby forming a gate stack having a convex top surface that includes a first top surface of the first layer and a second top surface of the second layer.
15. The method of claim 14 , wherein the selective removing process includes a selective chemical mechanical polishing (CMP) process, wherein the selective CMP process uses a slurry having chemicals to provide selective removal rates to the plurality of metal layers.
16. The method of claim 14 , wherein the selective removing process includes a selective etching process, wherein the selective etching process uses an etchant having selective etching rates to the plurality of metal layers.
17. The method of claim 16 , wherein the etchant includes a chemical selected from the group consisting of F2, C12, BCl3, and a combination thereof.
18. The method of claim 14 , wherein the forming a plurality of gate material layers includes forming
a gate dielectric layer including a high k dielectric material;
a capping layer disposed over the high k dielectric material layer;
a work function metal layer disposed over the capping layer;
a blocking layer disposed over the work function metal layer; and
a metal layer disposed over the blocking layer.
19. The method of claim 14 , further comprising forming a top capping layer over the convex top surface of the gate stack in edge areas, wherein the forming of the top capping layer includes depositing a dielectric layer over the substrate and the gate stack; and performing a chemical mechanical polishing process to the top capping layer such that the first top surface of the first layer extends through the top capping layer.
20. The method of claim 19 , wherein the depositing of the top capping layer includes depositing a dielectric material layer selected from the group consisting of silicon oxide, silicon nitride, low-k dielectric material, and a combination thereof.