IP Library › Granted Patent US 9,880,222
Granted Patent B2
US 9,880,222 · App. 15/176,874 · Granted Jan 30, 2018

Testing TSV with current/voltage source, resistor, comparator, and scan cell

Inventors: Lee D. Whetsel (Parker, TX); Baher S. Haroun (Allen, TX)
Assignee: Texas Instruments Incorporated
G01R31/3177G01R31/26G01R31/31723G01R31/318505G01R31/318577
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Quick Facts
Patent No.
US 9,880,222
App. No.
15/176,874
Granted
Jan 30, 2018
Kind
B2
Abstract

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Claims (12)

1. A test cell for providing test stimulus and receiving test response on a single signal path coupled to a through silicon via comprising:

(a) a stimulus current source having an output coupled to the single signal path and having a control input for controlling supplying stimulus current to the single signal path and not supplying stimulus current to the single signal path;

(b) a resistor in the single signal path having a first terminal connected to the output of the stimulus current source and a second terminal;

(c) a comparator having a first input connected to the second terminal of the resistor for receiving test response from the single signal path, a second input for receiving a voltage reference and an output;

(d) a scan cell having a scan input, a capture input coupled to the comparator output, a control output coupled to the control input of the stimulus current source, and a scan output; and

(e) the through silicon via having a first end connected to the second terminal of the resistor and the first input of the comparator, and having a second end connected to a circuit ground.

2. A test cell for providing test stimulus and receiving test response on a single signal path coupled to a through silicon via comprising:

(a) a stimulus voltage source having an output coupled to the single signal path and having a control input for controlling supplying stimulus current to the single signal path and not supplying stimulus current to the single signal path;

(b) a resistor in the single signal path having a first terminal connected to the output of the stimulus current source and a second terminal;

(c) a comparator having a first input connected to the second terminal of the resistor for receiving test response from the single signal path, a second input for receiving a voltage reference and an output;

(d) a scan cell having a scan input, a capture input coupled to the comparator output, a control output coupled to the control input of the stimulus current source, and a scan output; and

(e) the through silicon via having a first end connected to the second terminal of the resistor and the first input of the comparator, and having a second end connected to a circuit ground.

Continuity (4)
Division 13785284 · Mar 5, 2013
Provisional Application 61670793 · Jul 12, 2012
Provisional Application 61613235 · Mar 20, 2012
Related Publication 20160282411A1 · Sep 29, 2016