IP Library › Granted Patent US 9,881,911
Granted Patent B2
US 9,881,911 · App. 13/801,354 · Granted Jan 30, 2018

Electronic system having increased coupling by using horizontal and vertical communication channels

Inventor: Alberto Pagani (Nova Milanese, IT)
Assignee: STMicroelectronics S.r.l.
H01L27/0203H01L21/6835H01L21/768H01L23/3128H01L23/48H01L23/66H01L24/06H01L24/08H01L24/09H01L24/14H01L24/19H01L24/20H01L24/30H01L24/73H01L24/94H01L24/95H01L25/0657H01L25/105H05K1/181H01L21/561H01L21/568H01L22/22H01L23/49833H01L24/05H01L24/13H01L24/16H01L24/29H01L24/32H01L24/48H01L2221/68304H01L2223/6677H01L2224/02313H01L2224/02319H01L2224/02321H01L2224/02371H01L2224/0401H01L2224/04105H01L2224/05569H01L2224/06187H01L2224/08137H01L2224/08146H01L2224/12105H01L2224/13024H01L2224/14183H01L2224/16145H01L2224/16225H01L2224/16227H01L2224/211H01L2224/2105H01L2224/28105H01L2224/29024H01L2224/30183H01L2224/32145H01L2224/32227H01L2224/48091H01L2224/48175H01L2224/73207H01L2224/73215H01L2224/73251H01L2224/82106H01L2224/94H01L2224/95H01L2225/06531H01L2225/06541H01L2225/06555H01L2225/06565H01L2225/06568H01L2225/06572H01L2225/06596H01L2225/107H01L2225/1023H01L2225/1064H01L2924/00014H01L2924/12042H01L2924/15159H05K1/189H05K2201/10515Y02P70/611
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Quick Facts
Patent No.
US 9,881,911
App. No.
13/801,354
Granted
Jan 30, 2018
Kind
B2
Abstract

An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Claims (14)

1. A system, comprising:

a first integrated circuit, including:

a first integrated circuit die;

a first metallization layer mounted to a top surface of the first integrated circuit die;

a first dielectric layer having a first side portion disposed in contact with a peripheral side surface of both the first integrated circuit die and the first metallization layer and further having a first non-side portion disposed in contact with a top surface of the first metallization layer, and

a first communication pad disposed along the first side portion; and

a second integrated circuit, including:

a second integrated circuit die;

a second metallization layer mounted to a top surface of the second integrated circuit die;

a second dielectric layer having a second side portion disposed in contact with a peripheral side surface of both the second integrated circuit die and the second metallization layer that is facing the first side portion and further having a second non-side portion disposed in contact with a top surface of the second metallization layer, and

a second communication pad disposed along the second side portion and coupled to the first communication pad.

2. The system of claim 1 wherein one of the first and second integrated circuits includes a computing circuit.

3. The system of claim 1 , further comprising a package within which the first and second integrated circuits are disposed.

4. The system of claim 1 , further comprising a circuit board disposed between the first side portion of the first dielectric layer and the second side portion of the second dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2013
From: PAGANI, ALBERTO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 029988/0823 →
Priority Claims (1)
IT VI2012A0060 · Mar 19, 2012 · national
Continuity (1)
Related Publication 20130241025A1 · Sep 19, 2013