Semiconductor device having asymmetrical source/drain

1. A semiconductor device, comprising:

a semiconductor substrate;

an active fin that vertically extends from the semiconductor substrate;

an asymmetric source/drain on an upper portion of the active fin,

wherein the asymmetric source/drain comprises a first crystal growth portion and a second crystal growth portion that extends from a portion of the first crystal growth portion,

wherein a lower surface of the second crystal growth portion is at lower level than a lower surface of the first crystal growth portion, and

wherein the asymmetric source/drain contacts only one sidewall of the active fin, and

wherein the lower surface of the second crystal growth portion is spaced apart from a device isolation layer that covers lower portions of the active fin by a spacer comprising a first material that is different from a second material comprising the device isolation layer.

2. The semiconductor device of claim 1 , wherein the first crystal growth portion contacts an upper surface of the upper portion of the active fin, and the second crystal growth portion contacts a first side surface of the upper portion of the active fin.

3. The semiconductor device of claim 2 , wherein the second crystal growth portion comprises a rectangular shape.

4. The semiconductor device of claim 1 , further comprising a gate stack that crosses the active fin, and

wherein the gate stack comprises a gate dielectric layer and a gate electrode.

5. The semiconductor device of claim 1 , wherein an extended direction of the second crystal growth portion is oblique to an extended direction of the active fin.

6. The semiconductor device of claim 1 , wherein the active fin comprises a first side surface and a second side surface opposite the first side surface,

wherein the second crystal growth portion contacts a portion of the second side surface and does not contact the first side surface.

7. The semiconductor device of claim 1 ,

wherein a lowest point of the lower surface of the second crystal growth portion is spaced apart from the active fin.

8. A semiconductor device, comprising:

a semiconductor substrate;

active fins that protrude from the semiconductor substrate;

a device isolation layer that fills between the active fins, wherein upper surfaces of the device isolation layer adjacent side surfaces of the active fins are at a low level, and wherein upper surfaces of the device isolation layer adjacent other side surfaces parallel to the side surfaces are at a high level that is a greater distance from the semiconductor substrate than the low level; and

asymmetric source/drains on the active fins,

wherein the asymmetric source/drains comprise first crystal growth portions that contact upper surfaces of the active fins, and second crystal growth portions that share at least one plane with the first crystal growth portions and contact side surfaces of the active fins,

wherein a lower surface of the second crystal growth portions are at a lower level than a lower surface of the first crystal growth portions,

wherein the lower surface of the second crystal growth portion is spaced apart from the device isolation layer that that fills between the active fins,

wherein a lowest point of the lower surface of the second crystal growth portions is spaced apart from the active fins, and

wherein the lower surface of the second crystal growth portion is spaced apart from the device isolation layer that covers lower portions of the active fin by a spacer comprising a first material that is different from a second material comprising the device isolation layer.

9. The semiconductor device of claim 8 , wherein the upper surfaces of the device isolation layer adjacent facing side surfaces of adjacent active fins are disposed at a same level.

10. The semiconductor device of claim 8 , further comprising gate stacks that cross the active fins,

wherein each of the gate stacks comprises a gate dielectric layer and a gate electrode,

wherein the gate dielectric layer comprises a lower surface that contacts the upper surface and extends along the upper surfaces of the device isolation layer, the upper surfaces of the active fins, and side surfaces perpendicular to the lower surface of the gate dielectric layer, and

wherein the gate electrode contacts the lower surface and the side surfaces of the gate dielectric layer.

11. The semiconductor device of claim 8 , further comprising:

a first trench shared by the active fins and that has a first width; and

a second trench that has a second width greater than the first width.

12. The semiconductor device of claim 11 , wherein side surfaces of the first trench and side surfaces of the second trench are the side surfaces of the active fins.

13. The semiconductor device of claim 12 , wherein the device isolation layer fills the first trench and the second trench, and

an upper surface of the device isolation layer adjacent the side surfaces of the first trench is at a higher level than an upper surface of the device isolation layer adjacent the side surfaces of the second trench.

14. A semiconductor device, comprising:

a semiconductor substrate;

active fins on the semiconductor substrate, wherein the active fins include a first active fin, a second active fin and a third active fin, wherein the second active fin is disposed between the first active fin and the third active fin, and wherein a distance between the second active fin and the third active fin is greater than a distance between the second active fin and the first active fin;

an isolation layer disposed between the active fines, wherein the isolation layer includes a first isolation region and a second isolation region, wherein the first isolation region is disposed between the first active fin and the second active fin, and wherein the second isolation region is disposed between the second active fin and the third active fin;

a first crystal growth source/drain on the first active fin;

a second crystal growth source/drain on the second active fin; and

a third crystal growth source/drain on the third active fin,

wherein the second crystal growth source/drain includes a first lower end portion in direct contact with the first isolation region and a second lower end portion in direct contact with the second isolation region,

wherein a width of the second isolation region is greater than a width of the first isolation region,

wherein the second lower end portion is at lower level than the first lower end portion,

wherein the second crystal growth source/drain comprises a main crystal growth portion on the second active fin and an additional crystal growth portion extended from a portion of the main crystal growth portion,

wherein the additional crystal growth portion is adjacent to the second isolation region, and

wherein the second lower end portion is a lower end portion of the additional growth portion, and the first lower end portion is a lower end portion of the main crystal growth portion.

15. The semiconductor device of claim 14 , wherein the second active fin comprises a first side surface and a second side surface opposite the first side surface, and

wherein the additional crystal growth portion contacts a portion of the second side surface and does not contact the first side surface.

16. The semiconductor device of claim 14 , wherein the second crystal growth source/drain is connected to the first crystal growth source/drain.

17. The semiconductor device of claim 16 , wherein the second crystal growth source/drain is spaced apart from the third crystal growth source/drain.