IP Library › Granted Patent US 9,887,150
Granted Patent B2
US 9,887,150 · App. 15/449,117 · Granted Feb 6, 2018

Semiconductor device

Inventors: Akihiro Koga (Kyoto, JP); Taro Nishioka (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01L23/49548H01L23/293H01L23/3107H01L23/3114H01L23/49H01L23/4952H01L23/49503H01L23/49541H01L24/42H01L24/48H01L24/49H01L24/32H01L2224/32245H01L2224/48091H01L2224/48106H01L2224/48177H01L2224/48247H01L2224/49H01L2224/73265H01L2924/00014H01L2924/01004H01L2924/1715H01L2924/181
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,887,150
App. No.
15/449,117
Granted
Feb 6, 2018
Kind
B2
Abstract

A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Claims (51)

1. A semiconductor device comprising:

a semiconductor chip;

an island having an upper surface to which the semiconductor chip is bonded;

first, second, third and fourth leads arranged around the island;

a bonding wire extending between a surface of the semiconductor chip and an upper surface of the first, second, third and fourth leads; and

a resin package collectively sealing the semiconductor chip, the island, the first, second, third and fourth leads and the bonding wire, wherein the resin package has first, second, third and fourth sides in a bottom plan view of the device in which the first and second sides are connected to each other;

wherein a lower surface of the island and lower surfaces of the first, second, third and fourth leads are exposed on a rear surface of the resin package;

wherein first, second, third and fourth sides of the island define an area, each of the first, second, third and fourth sides of the island is non-parallel to each of the first, second, third and fourth sides of the resin package, in the bottom plan view;

wherein each of the first, second, third and fourth leads has a first side which is parallel with the first side of the resin package in the bottom plan view;

wherein each of the first, second, third and fourth leads has a second side which is parallel with the second side of the resin package in the bottom plan view;

wherein for each respective lead of the first, second, third and fourth leads, the first side of the respective lead and the second side of the respective lead are connected to each other in the bottom plan view;

wherein for each respective lead of the first, second, third and fourth leads, a side surface of the first side of the respective lead is exposed on a side surface of the resin package in the bottom plan view;

wherein the second side of the first lead, that is closer to the second side of the resin package than the second side of another of the second, third and fourth leads is to the second side of the resin package, faces the second side of the resin package with a distance therebetween in the bottom plan view;

wherein each of the first, second, third and fourth leads has a third side which is non-parallel with each of the first, second, third and fourth sides of the resin package in the bottom plan view;

wherein in the bottom plan view, the semiconductor device further comprises a facing portion including

one of the first, second, third, and fourth sides of the island, and

the third side of one of the first, second, third and fourth leads,

wherein in the bottom plan view, the one of the first, second, third, and fourth sides of the island faces and is parallel to the third side of the one of the first, second, third and fourth leads.

2. The semiconductor device according to claim 1 , wherein the facing portion includes an etched portion such that the one of the first, second, third, and fourth sides of the island and the third side of the one of the first, second, third and fourth leads includes a non-parallel portion in which a part of the one of the first, second, third, and fourth sides of the island is non-parallel to a part of the third side of the one of the first, second, third and fourth leads.

3. The semiconductor device according to claim 2 , wherein the etched portion is formed at a position apart from a corner of the facing portion.

4. The semiconductor device according to claim 2 , wherein the etched portion is arcuately shaped in the bottom plan view.

5. The semiconductor device according to claim 2 , wherein the etched portion includes a coming-off preventing portion below which a part of the resin package infiltrates in a sectional plan view.

6. The semiconductor device according to claim 5 , wherein the coming-off preventing portion has a portion parallel to a lower surface of the semiconductor device.

7. The semiconductor device according to claim 5 , wherein the coming-off preventing portion is held by the resin package from both of upper and lower sides thereof.

8. The semiconductor device according to claim 1 , wherein each respective lead of the first, second, third and fourth leads further comprises a fourth side which connects the third side of the respective lead and the first side of the respective lead in the bottom plan view.

9. The semiconductor device according to claim 1 , wherein each respective lead of the first, second, third and fourth leads further comprises a fifth side which connects the third side of the respective lead and the second side of the respective lead in the bottom plan view.

10. The semiconductor device according to claim 2 , wherein at least part of the etched portion has a partial circle shape in the bottom plan view.

11. The semiconductor device according to claim 2 , wherein the etched portion has a partial circle shape at an edge line of the etched portion in the bottom plan view.

12. The semiconductor device according to claim 1 , wherein a non-parallel portion, in which a part of the one of the first, second, third, and fourth sides of the island is non-parallel to a part of the third side of the one of the first, second, third and fourth leads, is formed in the facing portion between the third side of the one of the first, second, third and fourth leads and the one of the first, second, third, and fourth sides of the island.

13. The semiconductor device according to claim 12 , wherein the facing portion includes an etched portion, and the etched portion is formed at a position apart from a corner of the facing portion.

14. The semiconductor device according to claim 12 , wherein the facing portion includes an etched portion, and the etched portion is arcuately shaped in the bottom plan view.

15. The semiconductor device according to claim 12 , wherein the facing portion includes an etched portion, and the etched portion includes a coming-off preventing portion below which a part of the resin package infiltrates in a sectional plan view.

16. The semiconductor device according to claim 15 , wherein the coming-off preventing portion has a portion parallel to a lower surface of the semiconductor device.

17. The semiconductor device according to claim 15 , wherein the coming-off preventing portion is held by the resin package from both of upper and lower sides thereof.

18. The semiconductor device according to claim 15 , wherein each respective lead of the first, second, third and fourth leads further comprises a fourth side which connects the third side of the respective lead and the first side of the respective lead in the bottom plan view.

19. The semiconductor device according to claim 1 , wherein the first, second, third and fourth leads are arranged at corners of the semiconductor device in the bottom plan view, respectively.

20. The semiconductor device according to claim 1 , wherein the one of the first, second, third, and fourth sides of the island which forms the facing portion, has an etched portion.

21. The semiconductor device according to claim 1 , wherein the first, second, third and fourth leads are arranged proximate corners of the semiconductor device in the bottom plan view, respectively.

22. A semiconductor device comprising:

a semiconductor chip;

an island having an upper surface to which the semiconductor chip is bonded, the island having an area defined by first, second, third and fourth sides in a bottom plan view, the first side of the island having a first portion which is etched, and a second portion;

four leads arranged around the island, in a bottom plan view each of the leads having first and second sides connected to each other;

a bonding wire extending between a surface of the semiconductor chip and an upper surface of the leads; and

a resin package collectively sealing the semiconductor chip, the island, the leads and the bonding wire, in the bottom plan view the resin package having first, second, third and fourth sides, in the bottom plan view, each of the first, second, third and fourth sides of the resin package is non-parallel to each of the first, second, third and fourth sides of the island, the first side of the resin package and the second side of the resin package are connected to each other;

wherein each of the first sides of the leads is parallel with the first side of the resin package in the bottom plan view;

wherein each of the second sides of the leads is parallel with the second side of the resin package in the bottom plan view;

wherein for each respective lead of the leads, a side surface of the first side of the respective lead is exposed on a side surface the resin package in the bottom plan view;

wherein the second side of one of the leads, which is closer to the second side of the resin package than the second side of another of the leads is to the second side of the resin package, is facing the second side of the resin package with a distance therebetween in the bottom plan view;

wherein each of the leads has a third side which is non-parallel with each of the first, second, third and fourth sides of the resin package in the bottom plan view; and

wherein one of the third sides of the leads faces the first side of the island in the bottom plan view, the one of the third sides of the leads is parallel to the second portion of the first side of the island.

23. The semiconductor device according to claim 22 , wherein the four leads are arranged proximate corners of the semiconductor device in the bottom plan view, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2017
From: KOGA, AKIHIRO; NISHIOKA, TARO
To: ROHM CO., LTD.
Reel/Frame 041460/0962 →
Priority Claims (1)
JP 2008-326113 · Dec 22, 2008 · national
Continuity (6)
Continuation 15093825 · Apr 8, 2016
Continuation 14637565 · Mar 4, 2015
Continuation 14257217 · Apr 21, 2014
Continuation 13930670 · Jun 28, 2013
Division 13141222
Related Publication 20170179006A1 · Jun 22, 2017