IP Library › Granted Patent US 9,887,212
Granted Patent B2
US 9,887,212 · App. 14/637,557 · Granted Feb 6, 2018

Semiconductor device and electronic device

Inventors: Hajime Kimura (Kanagawa, JP); Tomoaki Atsumi (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1222G11C11/24G11C11/56G11C11/565G11C11/5685G11C13/0002G11C13/003G11C13/0007H01L27/1225H01L29/7869G11C2213/53G11C2213/74G11C2213/79
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,887,212
App. No.
14/637,557
Granted
Feb 6, 2018
Kind
B2
Abstract

A semiconductor device that can store multilevel data is provided. A circuit includes a transistor. The circuit includes another circuit including a terminal, for example. The terminal is connected to a gate of the transistor. One of a source and a drain of the transistor is connected to a wiring, and the other of the source and the drain is connected to another wiring.

Claims (128)

1. A semiconductor device comprising:

a memory cell array comprising memory cells, each of the memory cells comprising:

a first transistor;

a first circuit comprising:

a second transistor;

a third transistor; and

a first capacitor; and

a second circuit comprising:

a fourth transistor;

a fifth transistor; and

a second capacitor,

wherein a first terminal of the first transistor is electrically connected to a circuit configured to read a signal via a first wiring,

wherein a second terminal of the first transistor is electrically connected to a second wiring,

wherein a gate of the first transistor is electrically connected to a first terminal of the first circuit,

wherein the gate of the first transistor is electrically connected to a first terminal of the second circuit,

wherein a first terminal of the second transistor is electrically connected to the first terminal of the first circuit,

wherein a gate of the second transistor is electrically connected to a first terminal of the first capacitor,

wherein a first terminal of the third transistor is electrically connected to the gate of the second transistor,

wherein a first terminal of the fourth transistor is electrically connected to the first terminal of the second circuit,

wherein a gate of the fourth transistor is electrically connected to a first terminal of the second capacitor,

wherein a first terminal of the fifth transistor is electrically connected to the gate of the fourth transistor,

wherein the first transistor comprises single crystal silicon in its channel formation region, and

wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor each comprise an oxide semiconductor in their channel formation regions.

2. The semiconductor device according to claim 1 , further comprising a third capacitor, wherein a first terminal of the third capacitor is electrically connected to the gate of the first transistor.

3. The semiconductor device according to claim 1 , further comprising a sixth transistor, wherein a first terminal of the sixth transistor is electrically connected to the gate of the first transistor.

4. The semiconductor device according to claim 1 ,

wherein a second terminal of the second transistor is electrically connected to a second terminal of the third transistor, and

wherein a second terminal of the fourth transistor is electrically connected to a second terminal of the fifth transistor.

5. The semiconductor device according to claim 1 ,

wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor each have a same polarity, and

wherein the first transistor has a polarity different from a polarity of the second transistor.

6. The semiconductor device according to claim 1 , wherein an amplitude of a potential of the gate of the first transistor is smaller than an amplitude of a potential of the gate of the second transistor.

7. The semiconductor device according to claim 1 ,

wherein the first circuit is configured to store data of one bit or more, and

wherein the second circuit is configured to store data of one bit or more.

8. An electronic device comprising:

the semiconductor device according to claim 1 , and

a display device.

9. A semiconductor device comprising:

a memory cell array comprising memory cells, each of the memory cells comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a first capacitor;

a second capacitor; and

a third capacitor,

wherein a first terminal of the first transistor is electrically connected to a circuit configured to read a signal via a first wiring,

wherein a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a gate of the first transistor,

wherein a first terminal of the third capacitor is electrically connected to the gate of the first transistor,

wherein a gate of the second transistor is electrically connected to a first terminal of the first capacitor,

wherein a first terminal of the third transistor is electrically connected to the gate of the second transistor,

wherein a first terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a first terminal of the second capacitor, and

wherein a first terminal of the fifth transistor is electrically connected to the gate of the fourth transistor.

10. The semiconductor device according to claim 9 ,

wherein a second terminal of the second transistor is electrically connected to a second terminal of the third transistor, and

wherein a second terminal of the fourth transistor is electrically connected to a second terminal of the fifth transistor.

11. The semiconductor device according to claim 9 ,

wherein the first transistor comprises single crystal silicon in its channel formation region, and

wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor each comprise an oxide semiconductor in their channel formation regions.

12. The semiconductor device according to claim 9 ,

wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor each have a same polarity, and

wherein the first transistor has a polarity different from a polarity of the second transistor.

13. The semiconductor device according to claim 9 , wherein an amplitude of a potential of the gate of the first transistor is smaller than an amplitude of a potential of the gate of the second transistor.

14. An electronic device comprising:

the semiconductor device according to claim 9 , and

a display device.

15. A semiconductor device comprising:

a memory cell array comprising memory cells, each of the memory cells comprising:

a first transistor;

a second transistor;

a third transistor; and

a capacitor,

wherein a gate of the first transistor is electrically connected to a first terminal of the second transistor,

wherein a first terminal of the first transistor is electrically connected to a circuit configured to read a signal via a first wiring,

wherein a gate of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the capacitor,

wherein the first transistor comprises single crystal silicon in its channel formation region, and

wherein the second transistor and the third transistor each comprise an oxide semiconductor in their channel formation regions.

16. The semiconductor device according to claim 15 , wherein a polarity of the first transistor is different from those of the second transistor and the third transistor.

17. The semiconductor device according to claim 15 ,

wherein a second terminal of the second transistor is electrically connected to a second wiring, and

wherein a second terminal of the third transistor is electrically connected to a third wiring.

18. The semiconductor device according to claim 15 , wherein a second terminal of the second transistor and a second terminal of the third transistor are electrically connected to a second wiring.

19. The semiconductor device according to claim 15 , wherein the oxide semiconductor comprises indium, gallium, and zinc.

20. The semiconductor device according to claim 15 , comprising a fourth transistor, wherein the first transistor and the fourth transistor are electrically connected in series between the first wiring and a second wiring.

21. An electronic device comprising:

the semiconductor device according to claim 15 , and

a display device.

22. The semiconductor device according to claim 1 , wherein the first wiring has a function of a bit line.

23. The semiconductor device according to claim 9 , wherein the first wiring has a function of a bit line.

24. The semiconductor device according to claim 15 , wherein the first wiring has a function of a bit line.

25. A semiconductor device comprising:

a memory cell array comprising memory cells, each of the memory cells comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first capacitor; and

a second capacitor,

wherein a first terminal of the first transistor is electrically connected to a circuit configured to read a signal via a first wiring,

wherein a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a gate of the first transistor,

wherein a first terminal of the sixth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the second transistor is electrically connected to a first terminal of the first capacitor,

wherein a first terminal of the third transistor is electrically connected to the gate of the second transistor,

wherein a first terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a first terminal of the second capacitor, and

wherein a first terminal of the fifth transistor is electrically connected to the gate of the fourth transistor.

26. A semiconductor device according to claim 25 , further comprising a sixth transistor, wherein the first transistor and the seventh transistor are electrically connected in series to each other between the first wiring and the second wiring.

27. The semiconductor device according to claim 25 ,

wherein a second terminal of the second transistor is electrically connected to a second terminal of the third transistor, and

wherein a second terminal of the fourth transistor is electrically connected to a second terminal of the fifth transistor.

28. The semiconductor device according to claim 25 ,

wherein the first transistor comprises single crystal silicon in its channel formation region, and

wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor each comprise an oxide semiconductor in their channel formation regions.

29. The semiconductor device according to claim 25 ,

wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor each have a same polarity, and

wherein the first transistor has a polarity different from a polarity of the second transistor.

30. The semiconductor device according to claim 25 , wherein an amplitude of a potential of the gate of the first transistor is smaller than an amplitude of a potential of the gate of the second transistor.

31. An electronic device comprising:

the semiconductor device according to claim 25 , and

a display device.

32. The semiconductor device according to claim 25 , wherein the first wiring has a function of a bit line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2015
From: KIMURA, HAJIME; ATSUMI, TOMOAKI; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 035361/0585 →
Priority Claims (2)
JP 2014-051988 · Mar 14, 2014 · national
JP 2014-052001 · Mar 14, 2014 · national
Continuity (1)
Related Publication 20150263047A1 · Sep 17, 2015