IP Library Granted Patent US 9,887,293
Granted Patent B2
US 9,887,293 · App. 15/191,542 · Granted Feb 6, 2018

Semiconductor device

Inventors: Zhibiao Zhou (Singapore, SG); Ding-Lung Chen (Singapore, SG); Chen-Bin Lin (Taipei, TW); Sanpo Wang (Singapore, SG); Chung-Yuan Lee (Taoyuan, TW); Chi-Fa Ku (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/78609H01L29/788H01L29/7869H01L29/78648H01L29/792
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Quick Facts
Patent No.
US 9,887,293
App. No.
15/191,542
Granted
Feb 6, 2018
Kind
B2
Abstract

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

Claims (19)

1. A semiconductor device, comprising:

a substrate;

an oxide-semiconductor layer on a first gate electrode on said substrate;

two source/drain regions on said oxide-semiconductor layer;

a first dielectric layer covering on said oxide-semiconductor layer and said two source/drain regions;

a second gate electrode between said two source/drain regions and partially covering said oxide-semiconductor layer; and

a charge storage structure on said second gate electrode.

2. The semiconductor device of claim 1 , further comprising:

a sealing layer on said substrate and covering the sidewall of said charge storage structure.

3. The semiconductor device of claim 2 , wherein said sealing layer covers said oxide-semiconductor layer, said two source/drain regions, said charge storage structure and said second gate electrode.

4. The semiconductor device of claim 2 , wherein said sealing layer comprises a dielectric material.

5. The semiconductor device of claim 1 , wherein said charge storage structure comprises an oxide-nitride-oxide structure.

6. The semiconductor device of claim 1 , wherein said charge storage structure comprises a floating gate.

7. The semiconductor device of claim 6 , further comprising:

a second dielectric layer between said second gate electrode and said floating gate.

8. The semiconductor device of claim 6 , wherein said floating gate covers said first gate electrode in a projection direction.

9. The semiconductor device of claim 6 , further comprising:

a conductive layer on said floating gate.

10. The semiconductor device of claim 9 , wherein said conductive layer is provided with a conductive material different from the material of said second gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2016
From: ZHOU, ZHIBIAO; CHEN, DING-LUNG; LIN, CHEN-BIN; WANG, SANPO; LEE, CHUNG-YUAN; KU, CHI-FA
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 039001/0032 →
Priority Claims (1)
TW 105115666 A · May 20, 2016 · national
Continuity (1)
Related Publication 20170338351A1 · Nov 23, 2017