Reducing pin count requirements for implementation of interconnect idle states
Methods and apparatus relating to reducing pin count requirements for implementation of interconnect idle state(s) are described. In one embodiment, logic receives a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal. An I/O device (e.g., coupled to the I/O complex logic) enters a low power consumption state in response to the control signal. The logic receives a wake signal on the signal pin of the I/O complex logic and the I/O device exits the low power consumption state in response to the wake signal. Other embodiments are also claimed and disclosed.
1. An apparatus comprising:
logic, the logic at least partially comprising hardware logic, to receive a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal, wherein an I/O device coupled to the I/O complex logic is to enter a low power consumption state in response to the control signal,
wherein the logic to receive the general purpose input signal is to receive a wake signal on the signal pin of the I/O complex logic, wherein the I/O device is to exit the low power consumption state in response to the wake signal, wherein the I/O device is to communicate with the I/O complex logic only through the logic to receive the general purpose input signal.
2. The apparatus of claim 1 , wherein the I/O complex logic is to stop transmission of one or more clock signals to the I/O device in response to the control signal.
3. The apparatus of claim 1 , wherein the I/O complex logic is to start transmission of one or more clock signals to the I/O device in response to the wake signal.
4. The apparatus of claim 1 , wherein the I/O complex logic is to generate one or more general purpose input output signals in response to an indication from software.
5. The apparatus of claim 4 , wherein a Basic Input Output System (BIOS) is to configure the one or more general purpose input output signals.
6. The apparatus of claim 1 , wherein the I/O device is to wait for expiration of a timer prior to exit from the low power consumption state.
7. The apparatus of claim 1 , wherein the low power consumption state is compliant with a run time D3 state.
8. The apparatus of claim 1 , further comprising memory to store operating system software, wherein the operating system software is to control a power state of the I/O device via one or more general purpose input output signals.
9. The apparatus of claim 1 , wherein the logic, one or more processor cores, and memory are located on a single integrated circuit die.
10. A method comprising:
receiving, at a first logic, a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal, wherein an I/O device coupled to the I/O complex logic is to enter a low power consumption state in response to the control signal,
wherein a wake signal received on the signal pin of the I/O complex logic causes the I/O device to exit the low power consumption state, wherein the I/O device communicates with the I/O complex logic only through the first logic.
11. The method of claim 10 , further comprising the I/O complex logic stopping transmission of one or more clock signals to the I/O device in response to the control signal.
12. The method of claim 10 , further comprising the I/O complex logic starting transmission of one or more clock signals to the I/O device in response to the wake signal.
13. The method of claim 10 , further comprising the I/O complex generating one or more general purpose input output signals in response to an indication from software.
14. The method of claim 13 , further comprising a Basic Input Output System (BIOS) configuring the one or more general purpose input output signals.
15. The method of claim 10 , further comprising the I/O device waiting for expiration of a timer prior to exit from the low power consumption state.
16. The method of claim 10 , further comprising storing operating system software in memory, wherein the operating system software controls a power state of the I/O device via one or more general purpose input output signals.
17. A system comprising:
an I/O complex logic to generate one or more general purpose input output signals;
logic, the logic at least partially comprising hardware logic, to receive a general purpose input signal on a signal pin of the I/O complex logic in response to a control signal, wherein an I/O device coupled to the I/O complex logic is to enter a low power consumption state in response to the control signal,
wherein the logic to receive the general purpose input signal is to receive a wake signal on the signal pin of the I/O complex logic, wherein the I/O device is to exit the low power consumption state in response to the wake signal, wherein the I/O device is to communicate with the I/O complex logic only through the logic to receive the general purpose input signal.
18. The system of claim 17 , wherein the I/O complex logic is to stop transmission of one or more clock signals to the I/O device in response to the control signal.
19. The system of claim 17 , wherein the I/O complex logic is to start transmission of one or more clock signals to the I/O device in response to the wake signal.
20. The system of claim 17 , wherein the I/O complex logic is to generate one or more general purpose input output signals in response to an indication from software.
21. The system of claim 20 , wherein a Basic Input Output System (BIOS) is to configure the one or more general purpose input output signals.
22. The system of claim 17 , wherein the I/O device is to wait for expiration of a timer prior to exit from the low power consumption state.
23. The system of claim 17 , wherein the low power consumption state is compliant with a run time D3 state.
24. The system of claim 1 further comprising memory to store operating system software, wherein the operating system software is to control a power state of the I/O device via one or more general purpose input output signals.
25. The system of claim 17 , wherein the logic, one or more processor cores, and memory are located on a single integrated circuit die.