IP Library Granted Patent US 9,892,080
Granted Patent B2
US 9,892,080 · App. 14/967,959 · Granted Feb 13, 2018

Receive mode upon expiration of UART transmit start BIT delay

Inventors: Schuyler T. Patton, Jr. (Dallas, TX); Punya Prakash (Dallas, TX); Melissa Marie Watkins (Dallas, TX); Saqib Nadeem Mohammad (Sandy Springs, GA); Bradley James Griffis (Schaumburg, IL)
Assignee: Texas Instruments Incorporated
G06F13/4072G06F13/4282H04B1/401H04B1/48H04B1/54H04L5/16
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Quick Facts
Patent No.
US 9,892,080
App. No.
14/967,959
Granted
Feb 13, 2018
Kind
B2
Abstract

Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the integrated circuit separately from a host processor of the integrated circuit with which the transceiver communicates. This can avoid slow transceiver turn-around times that may be associated with host processor control of the mode transitions.

Claims (16)

1. A process of operating an integrated circuit comprising:

monitoring, in logic circuitry separate from host processor circuitry, a transmit data output of a UART for a start bit;

starting a timer in the logic circuitry and selecting a transmit mode output from the logic circuitry upon monitoring a start bit on the transmit data output;

selecting a receive mode output from the logic circuitry upon expiration of the timer;

beginning a delay before the selecting;

monitoring the transmit data output of the UART for another start bit during the delay; and

proceeding to the selecting upon expiration of the delay.

2. The process of claim 1 including, upon expiration of the timer, beginning a delay before the selecting.

3. The process of claim 1 including, upon expiration of the timer, beginning a delay before the selecting and monitoring the transmit data output of the UART for another start bit.

4. A process of operating an integrated circuit comprising:

monitoring, in logic circuitry separate from host processor circuitry, a transmit data output of a UART for a start bit;

starting a timer in the logic circuitry and selecting a transmit mode output from the logic circuitry upon monitoring a start bit on the transmit data output;

selecting a receive mode output from the logic circuitry upon expiration of the timer;

beginning a delay before the selecting;

monitoring the transmit data output of the UART for another start bit during the delay; and

again starting the timer in the logic circuitry and selecting the transmit mode output from the logic circuitry upon monitoring another start bit on the transmit data output.

Continuity (3)
Division 14311355 · Jun 23, 2014
Provisional Application 61941922 · Feb 19, 2014
Related Publication 20160098373A1 · Apr 7, 2016