Cell structure for dual-port static random access memory

1. A dual port static random access memory (SRAM) cell comprising:

a write port portion, wherein the write port portion further includes

a first pull up device (WPU 1 ) and a second pull up device (WPU 2 );

a first pull down device (WPD 1 ) and a second pull down device (WPD 2 ); and

a first pass gate device (WPG 1 ) and a second pass gate device (WPG 2 ), wherein the WPU 1 , WPU 2 , WPD 1 and WPD 2 are configured to form two cross-coupled inverters for data storage, wherein the WPG 1 and WPG 2 are connected to the two cross-coupled inverters for writing; and

a read port portion, wherein the read port portion further includes a read pull down device (RPD) and a read pass gate device (RPG) connected to the two cross-coupled inverters for reading, wherein

each of the WPU 1 and WPU 2 includes a single fin field-effect transistor (FinFET),

each of the WPD 1 , WPD 2 , WPG 1 , WPG 2 , RPD and RPG includes multiple fin field-effect transistors (FinFETs),

each of the WPD 1 , WPD 2 , WPG 1 and WPG 2 includes the same number of FinFETs, and

the RPD includes a larger number of FinFETs than the RPG includes.

2. The dual port SRAM cell of claim 1 , wherein the numbers of FinFETs in the RPD and the RPG in the read port provides a ratio that is equal to 3/2.

3. The dual port SRAM cell of claim 2 , wherein the RPD includes three FinFETs and the RPD includes two FinFETs.

4. The dual port SRAM cell of claim 1 , wherein the RPD includes three FinFETs having a commonly connected source, a commonly connected drain, and a commonly connected gate.

5. The dual port SRAM cell of claim 4 , wherein the RPG includes two FinFETs having a common source, a common drain, and a common gate.

6. The dual port SRAM cell of claim 5 , wherein the three FinFETs in the RPD includes a first, second and third FinFETs formed on a first, second, and third fin active features, respectively, wherein

the first fin active feature is spaced a first distance S1 from the second fin active feature in a first direction,

the second fin active feature is spaced a second distance S2 from the third fin active feature in the first direction, and

the second distance S2 is different from the first distance S1.

7. The dual port SRAM cell of claim 6 , wherein the S1 and S2 has a ratio S1/S2 greater than 1.2.

8. The dual port SRAM cell of claim 6 , wherein the two FinFETs in the RPG are formed on the second and the third fin active features.

9. The dual port SRAM cell of claim 8 , wherein

the first fin active feature extends a first length in a second direction being orthogonal to the first direction;

the second fin active feature extends a second length in the second direction;

the third fin active feature extends a third length in the second direction;

each of the second and third lengths is greater than the first length.

10. The dual port SRAM cell of claim 8 , wherein

the first fin active feature has a discontinuous structure with one end overlapped with a gate of the RPG in a top view;

the second fin active feature has a continuous structure extending to multiple SRAM cells; and

the third fin active feature has a continuous structure extending to multiple SRAM cells.

11. The dual port SRAM cell of claim 10 , wherein

the WPD 2 of the write port includes two FinFETs formed on two fin active features, respectively,

the two FinFET of the WPD 2 includes a commonly connected gate formed on the two fin active features, and

the commonly connected gate of the WPD 2 extends in the first direction to directly contact the commonly connected gate of the RPD.

12. The dual port SRAM cell of claim 11 , wherein the single FinFET of the WPU 2 includes a gate formed on a single fin active feature, wherein the gate of the WPU 2 extends in the first direction to directly contact the commonly connected gate of the WPD 2 .

13. The dual port SRAM cell of claim 12 , wherein

the two fin active features extend in the second direction; and

the two FinFETs of the WPG 2 are formed on the two fin active features.

14. A dual port static random access memory (SRAM) cell comprising:

two cross-coupled inverters for date storage, wherein the two cross-coupled inverters include a first pull up device (WPU 1 ), a second pull up device (WPU 2 ), a first pull down device (WPD 1 ) and a second pull down device (WPD 2 );

a write port that includes a first pass gate device (WPG 1 ) and a second pass gate device (WPG 2 ) connected to the two cross-coupled inverters for writing; and

a read port that includes a read pull down device (RPD) and a read pass gate device (RPG) connected to the two cross-coupled inverters for reading, wherein the RPD includes three fin field-effect transistors (FinFETs), and the RPG includes two FinFETs.

15. The dual port SRAM cell of claim 14 , wherein the three FinFETs in the RPD includes a commonly connected source, a commonly connected drain, and a commonly connected gate.

16. The dual port SRAM cell of claim 15 , wherein the two FinFETs in the RPG includes a common source, a common drain, and a common gate.

17. The dual port SRAM cell of claim 16 , wherein the three FinFETs in the RPD includes a first, second and third FinFETs formed on a first, second, and third fin active features, respectively, wherein

the first fin active feature is spaced a first distance S1 from the second fin active feature in a first direction,

the second fin active feature is spaced a second distance S2 from the third fin active feature in the first direction, and

the second distance S2 is different from the first distance S1.

18. The dual port SRAM cell of claim 17 , wherein the 51 and S2 has a ratio S1/S2 greater than 1.2.

19. The dual port SRAM cell of claim 17 , wherein the two FinFETs in the RPG are formed on the second and the third fin active features.

20. A dual port static random access memory (SRAM) cell comprising:

two cross-coupled inverters for date storage, wherein the two cross-coupled inverters include a first pull up device (WPU 1 ), a second pull up device (WPU 2 ), a first pull down device (WPD 1 ) and a second pull down device (WPD 2 );

a write port that includes a first pass gate device (WPG 1 ) and a second pass gate device (WPG 2 ) connected to the two cross-coupled inverters for writing;

a read port that includes a read pull down device (RPD) and a read pass gate device (RPG) connected to the two cross-coupled inverters for reading, wherein the RPD includes three fin field-effect transistors (FinFETs), and the RPG includes two FinFETs; and

a first, second and third fin active features disposed within a read port, wherein

the first fin active feature has a discontinuous structure,

the second and third active features each have a continuous structure that extends to two adjacent SRAM cell,

the second fin active feature is spaced a first distance from the first fin active feature and is spaced a second distance from the third fin active feature, the second distance being less than the first distance,

the RPD includes three fin field-effect transistors (FinFETs) formed on the first, second and third fin active features, respectively, and

the RPG includes two FinFETs formed on the second and third fin active features, respectively.