IP Library › Granted Patent US 9,892,915
Granted Patent B2
US 9,892,915 · App. 15/285,570 · Granted Feb 13, 2018

Hard mask composition, carbon nanotube layer structure, pattern forming method, and manufacturing method of semiconductor device

Inventors: Seung Yun Yang (Miryang-si, KR); Seung Hyun Lee (Busan, KR); Kyoung Sil Park (Seongnam-si, KR); Yool Kang (Yongin-si, KR); Yi Seul Kim (Daejeon, KR); Yun Seok Choi (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/0271H01L21/02115H01L21/02282H01L21/02359H01L21/3081
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Quick Facts
Patent No.
US 9,892,915
App. No.
15/285,570
Granted
Feb 13, 2018
Kind
B2
Abstract

A manufacturing method of a semiconductor device includes forming a hard mask layer on a semiconductor substrate using a hard mask composition. Hard mask patterns are formed by patterning the hard mask layer. Semiconductor patterns are formed by etching the semiconductor substrate using the hard mask patterns. The hard mask composition includes a plurality of first carbon nanotubes (CNTs) having a first length, a plurality of second CNTs having a second length, which is at least 3 times the first length, and a dispersing agent in which the first CNTs and the second CNTs are dispersed. The total mass of the first CNTs is 1 to 2.5 times the total mass of the second CNTs.

Claims (24)

1. A manufacturing method of a semiconductor device, the method comprising:

forming a hard mask layer on a semiconductor substrate using a hard mask composition;

forming hard mask patterns by patterning the hard mask layer; and

forming semiconductor patterns by etching the semiconductor substrate using the hard mask patterns, wherein:

the hard mask composition comprises a plurality of first carbon nanotubes (CNTs) having a first length, a plurality of second CNTs having a second length, which is at least 3 times the first length, and a dispersing agent in which the first CNTs and the second CNTs are dispersed, and

a total mass of the first CNTs is 1 to 2.5 times a total mass of the second CNTs.

2. The manufacturing method of claim 1 , wherein the first length is 150 nm to 300 nm.

3. The manufacturing method of claim 2 , wherein the second length is 1 μm to 10 μm.

4. The manufacturing method of claim 1 , wherein:

the hard mask composition further comprises a polymer binder; and

the polymer binder fills gaps among the first CNTs and the second CNTs during the forming of the hard mask layer.

5. The manufacturing method of claim 4 , wherein a weight ratio of the polymer binder to the hard mask composition is 20 wt % or less.

6. The manufacturing method of claim 4 , wherein a weight ratio of the polymer binder to the hard mask composition is ¼ times or less a weight ratio of the first CNTs and the second CNTs to the hard mask composition.

7. The manufacturing method of claim 1 , wherein the forming of the hard mask layer, comprises forming the hard mask layer to have a coating uniformity of 50 Å to 100 Å.

8. The manufacturing method of claim 1 , wherein the hard mask composition further comprises a surfactant.

9. A manufacturing method of a semiconductor device, the method comprising:

dispersing a plurality of first carbon nanotubes (CNTs) having a first length and a plurality of second CNTs having a second length, different from the first length, within a dispersing agent to produce a hard mask composition;

forming a layer of the hard mask composition on a semiconductor substrate;

forming hard mask patterns by patterning the hard mask layer; and

forming semiconductor patterns by etching the semiconductor substrate using the hard mask patterns.

10. The method of claim 9 , wherein the second length is at least 3 times greater than the first length.

11. The method of claim 9 , wherein a total mass of the first CNTs is 1 to 2.5 times a total mass of the second CNTs.

12. The method of claim 9 , further comprising dispersing a polymer binder with the first CNTs and the second CNTs in the dispersing agent.

13. The method of claim 12 , wherein a weight ratio of the polymer binder to the hard mask composition is 20 wt % or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2016
From: YANG, SEUNG YUN; LEE, SEUNG HYUN; PARK, KYOUNG SIL; KANG, YOOL; KIM, YI SEUL; CHOI, YUN SEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 039947/0034 →
Priority Claims (1)
KR 10-2015-0185961 · Dec 24, 2015 · national
Continuity (1)
Related Publication 20170186602A1 · Jun 29, 2017