Semiconductor device and fabrication method therefor

1. A method of fabricating a semiconductor device, the method comprising:

forming a dummy structure over a substrate;

forming conductive features on opposite sides of the dummy structure;

removing the dummy structure and a portion of the substrate beneath the dummy structure to form a trench, wherein removing the portion of the substrate exposes a portion of the conductive features; and

filling the trench with a dielectric material.

2. The method of claim 1 , wherein the filling of the trench with a dielectric material comprises:

filling a first portion of the trench with a first dielectric material, and

filling a second portion of the trench with a second dielectric material different from the first dielectric material.

3. The method of claim 1 , further comprising planarizing the semiconductor device to expose a top surface of the dummy structure prior to the removing of the dummy structure.

4. The method of claim 1 , wherein the dielectric material and the conductive features form a capacitor.

5. The method of claim 1 , wherein removing the portion of the substrate comprises etching through an active layer to isolate a first well region and a second well region at opposite sides of the trench.

6. The method of claim 1 , wherein removing the dummy structure and the portion of the substrate comprises defining the trench comprising an upper portion above a top surface of the substrate and a lower portion below the top surface of the substrate, and the upper portion is aligned with the lower portion.

7. The method of claim 1 , wherein removing the dummy structure and the portion of the substrate comprises defining the trench having a width ranging from about 40 angstroms (Å) to about 200 Å.

8. A method of fabricating a semiconductor device, the method comprising:

forming a dummy gate structure over a substrate, wherein the dummy gate structure is an edge gate structure between a source/drain electrode of a first transistor and a source/drain electrode of a second transistor;

removing the dummy gate structure to define a first trench;

removing a portion of the substrate exposed by the first trench to form a second trench aligned with the first trench;

filling the first trench with a first dielectric material; and

filling the second trench with a second dielectric material different from the first dielectric material.

9. The method of claim 8 , wherein removing the portion of the substrate comprises removing the portion of the substrate and removing the dummy gate structure in a single etch process.

10. The method of claim 8 , wherein filling the first trench with the first dielectric material comprises filling the first trench with silicon nitride.

11. The method of claim 8 , further comprising:

connecting a gate of the first transistor to a word line; and

connecting the source/drain electrode of the second transistor to a reference voltage.

12. The method of claim 11 , further comprising connecting an additional source/drain electrode of the first transistor to a bit line, wherein the gate of the first transistor is between the additional source/drain electrode and the first dielectric material.

13. The method of claim 12 , wherein removing the portion of the substrate comprises defining the second trench having a bottom surface lower than a bottom surface of a well in the substrate.

14. The method of claim 13 , wherein filling the first trench with the first dielectric material comprises planarizing the first dielectric material to form a top surface of the first dielectric material co-planar with a top surface of the gate of the first transistor.

15. The method of claim 14 , wherein removing the dummy gate structure comprises forming the first trench having a width ranging from about 60 angstroms (Å) to about 100 Å.

16. A method of manufacturing a semiconductor device, the method comprising:

forming a first sacrificial gate structure and a second sacrificial gate structure over a fin structure, wherein the first sacrificial gate structure is over a first well region, and the second sacrificial gate structure is over an interface between the first well region and a second well region;

depositing an insulating material over the first sacrificial gate structure and the second gate sacrificial structure;

removing the first sacrificial gate structure to form a first trench;

removing the second sacrificial gate structure to form a second trench;

filling the first trench with a conductive material; and

filling the second trench with a dielectric material.

17. The method of claim 16 , wherein the removing of the first sacrificial gate structure to form the first trench comprises:

removing the first sacrificial gate structure until the fin structure is exposed.

18. The method of claim 16 , wherein the removing of the second sacrificial gate structure to form the second trench comprises:

removing the second sacrificial gate structure and a portion of the substrate beneath the second sacrificial gate structure, wherein a bottom surface of the second trench is below a bottom surface of the first well region.

19. The method of claim 16 , wherein the removing of the second sacrificial gate structure to form a second trench comprises:

using a photomask corresponding to a continuous poly on oxide definition edge (CPODE) pattern to define the second sacrificial gate structure.

20. The method of claim 16 , wherein the forming of the first sacrificial gate structure and the second sacrificial gate structure comprises:

forming the first sacrificial gate structure to have a same gate length as that of the second sacrificial gate structure.