Segmented field plate structure
A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
1. A method, comprising:
forming a transistor over a substrate;
depositing a dielectric layer over the transistor:
depositing a metal layer over the dielectric layer; and
patterning the metal layer to form a field plate having a notch located over a gate structure of the transistor, a plurality of contact pads connected to a source structure of the transistor, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
2. The method of claim 1 , wherein the notch has a width of about 5 um to 10 um.
3. The method of claim 1 , including forming a plurality of vias electrically connected to a source structure of the transistor, and patterning the metal layer to form the plurality of contact pads includes forming a contact pad over each via.
4. The method of claim 1 , wherein each one of the plurality of fingers has a width of about 5 um to 10 um and each one of the plurality of fingers are separated by at least about 5 um.
5. A method of forming a device, comprising:
forming a transistor over a substrate, the transistor including a source structure, a drain structure, and a gate structure;
depositing a dielectric layer over the transistor;
forming a plurality of vias electrically connected to the source structure;
depositing a metal layer over the dielectric layer; and
patterning the metal layer to form:
a field plate over the gate structure, the field plate including a notch over the gate structure,
a plurality of contact pads over each via, and
a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
6. The method of claim 5 , wherein each one of the formed plurality of fingers is directly connected to one and only one of contact pads.
7. The method of claim 5 , wherein each one of the formed plurality of fingers has a width of about 5 um to 10 um.
8. The method of claim 5 , wherein the formed plurality of fingers are separated from one another by at least about 5 um.
9. The method of claim 5 , wherein the notch has a width of about 5 um to 10 um.
10. The method of claim 5 , wherein the metal layer forms a metal contact over the substrate, the metal contact being electrically connected to the drain structure.
11. The method of claim 5 , wherein the transistor is a gallium nitride field effect transistor.
12. A method, comprising:
forming a transistor over a substrate;
depositing a dielectric layer over the transistor;
depositing a metal layer over the dielectric layer; and
patterning the metal layer to form:
a plurality of contact pads electrically connected to a first structure of the transistor,
a metal contact electrically connected to a second structure of the transistor, and
a field plate electrically connected to the plurality of contact pads and not electrically connected to the metal contact, the field plate including a notch over a gate structure of the transistor.
13. The method of claim 12 , wherein the metal layer includes a plurality of fingers connecting the field plate to each of the plurality of contact pads.
14. The method of claim 13 , wherein each one of the plurality of fingers has a width of about 5 um to 10 um.
15. The method of claim 13 , wherein each one of the plurality of fingers are separated by at least about 5 um.
16. The method of claim 12 , wherein the field plate defines an opening over a third structure of the transistor.
17. The method of claim 12 , wherein the notch has a width of about 5 um to 10 um.
18. The method of claim 12 , wherein the transistor is a gallium nitride field effect transistor.
19. The method of claim 12 , wherein the first structure is characterized as a source structure of the transistor, and the second structure is characterized as a drain structure of the transistor.