Fin field effect transistor fabrication and devices having inverted T-shaped gate
A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
1. A method of forming a fin field effect transistor (finFET), comprising:
forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer;
forming a gate spacer layer on each sidewall of the dummy gate layer;
forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer;
removing the dummy gate layer to expose the sacrificial gate layer;
removing the sacrificial gate layer to form a plurality of recessed cavities that exposes an inward facing sidewall of each of the source/drain spacer layers; and
forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
2. The method of claim 1 , wherein the gate structure occupying the plurality of recessed cavities forms an inverted T-shaped gate structure with a gate length greater than the width of the dummy gate layer.
3. The method of claim 1 , wherein the sacrificial gate layer is removed using an isotropic wet etch.
4. The method of claim 1 , further comprising:
forming a plurality of source/drains on one or more fins adjacent to the outward-facing sidewalls of the source/drain spacer layers; and
removing a portion of the outward-facing sidewalls of the source/drain spacer layer to form a step in the outward-facing sidewalls of the source/drain spacer layer.
5. The method of claim 4 , wherein the source/drain spacer layer is silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), or combinations thereof, and has a thickness in the range of about 4 nm to about 8 nm.
6. The method of claim 5 , wherein a portion of the source/drain spacer layer is removed using an isotropic wet etch.
7. The method of claim 4 , further comprising forming a metal liner on at least one of the plurality of source/drains and the step in the outward-facing sidewalls of the source/drain spacer layer.
8. The method of claim 7 , wherein the step in the outward-facing sidewalls of the source/drain spacer layer is at the same height as the top surface of source/drain.
9. The method of claim 7 , further comprising forming a source/drain fill on at least a portion of the metal liner, and forming a gate metal fill on at least a portion of the gate dielectric layer.
10. A method of forming a fin field effect transistor (finFET), comprising:
forming a sacrificial gate layer on one or more fins on a substrate;
forming a dummy gate layer on at least a portion of the sacrificial gate layer;
forming a gate spacer layer on the sidewalls of the dummy gate layer;
removing at least a portion of the sacrificial gate layer from a portion of the one or more fins;
forming a source/drain spacer layer on the outward-facing side rails of the gate spacer layers and the outward-facing sidewalls of the sacrificial gate layer;
removing the dummy gate layer to expose the inward-facing sidewalk of the gate spacer layers and the sacrificial gate layer between the gate spacer layers;
removing the remaining portion of the sacrificial gate layer on the one or more fins to form a plurality of recessed cavities; and
forming a gate structure on the one or more fins, wherein the gate structure occupies the plurality of recessed cavities.
11. The method of claim 10 , wherein the source/drain spacer layer is silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), or combinations thereof.
12. The method of claim 10 , further comprising forming a plurality of source/drains adjacent to the outward-facing sidewalk of the source/drain spacer layers on at least one of the one or more fins; and
removing a portion of the outward-facing sidewalls of each of the source/drain spacer layers to form a step in the outward-facing sidewalls.
13. The method of claim 12 , wherein the source/drains are epitaxially grown on at least one of the one or more fins.
14. The method of claim 12 , where the step is formed in the outward-facing sidewalls of each of the source/drain spacer layers using an isotropic wet etch.