Multi-level step-up converter topologies, control and soft start systems and methods
A multi-level, step-up converter circuit includes an inductor including one terminal in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the N transistor pair.
1. A system comprising:
an inductor including a first terminal in communication with an input voltage supply of a step-up converter;
N transistor pairs connected in series, where N is an integer greater than two, wherein first and second transistors of a first pair of the N transistor pairs are connected to a node, wherein the node is in communication with a second terminal of the inductor, and wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors connected between the N transistor pairs, respectively;
an output capacitor in communication with at least one transistor of the N transistor pairs; and
a controller configured to charge the (N−1) capacitors to voltages that are ratios of an output voltage of the step-up converter, wherein the ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.
2. The system of claim 1 wherein the controller is configured to sequentially:
charge a first one of the (N−1) capacitors to 1/N of the output voltage;
charge a second one of the (N−1) capacitors to 2/N of the output voltage; and
charge an (N−1)th one of the (N−1) capacitors to (N−1)/N of the output voltage.
3. The system of claim 1 wherein the controller is configured to initially charge the (N−1) capacitors to the input voltage before charging the (N−1) capacitors to the voltages that are ratios of the output voltage.
4. The system of claim 1 wherein the controller is configured to charge the (N−1) capacitors to the voltages that are ratios of the output voltage before operation of the step-up converter begins.
5. The system of claim 1 wherein the controller is configured to charge an (N−1) th one of the (N−1) capacitors to (N−1)/N of the output voltage.
6. The system of claim 1 wherein controller is configured to:
sense the voltages across the (N−1) capacitors; and
adjust duty cycles of the N transistor pairs to maintain the ratios of the voltages.
7. The system of claim 1 wherein controller is configured to:
sense current supplied by the inductor; and
transition between switching modes of the N transistor pairs based on the current supplied by the inductor.
8. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle less than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the first and third transistors are closed and the second and fourth transistors are open;
a second switching mode in which the first and second transistors are closed and the third and fourth transistors are open;
a third switching mode in which the second and fourth transistors are closed and the first and third transistors are open; and
a fourth switching mode in which the first and second transistors are closed and the third and fourth transistors are open.
9. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle less than 50%, the controller is configured to operate sequentially or non-sequentially in first, second, third, and fourth switching modes, and wherein:
during the first switching mode, current is supplied by at least one of the (N−1) capacitors to a load;
during the second switching mode, current is supplied by the inductor to the load;
during the third switching mode, at least one of the (N−1) capacitors is charged; and
during the fourth switching mode, current is supplied by the inductor to the load.
10. The system of claim 9 wherein the controller is configured to transition:
from the first switching mode to the second switching mode at D*T;
from the second switching mode to a third switching mode at T/2;
from the third switching mode to the fourth switching mode at (½+D)*T; and
from the fourth switching mode to the first switching mode at T, where T is a period and D is the duty cycle.
11. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle greater than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the first and third transistors are open and the second and fourth transistors are closed;
a second switching mode in which the second and third transistors are closed and the first and fourth transistors are open;
a third switching mode in which the first and third transistors are open and the second and fourth transistors are closed; and
a fourth switching mode in which the first and fourth transistors are closed and the second and third transistors are open.
12. The system of claim 1 wherein when operating in a continuous conduction mode with a duty cycle greater than 50%, the controller is configured to operate sequentially or non-sequentially in first, second, third, and fourth switching modes, and wherein:
during the first and third switching modes, current flows to ground;
during the second switching mode, current is supplied by at least one of the (N−1) capacitors to a load; and
during the fourth switching mode, at least one of the (N−1) capacitors is charged.
13. The system of claim 12 wherein the controller is configured to transition:
from the first switching mode to the second switching mode at (D−½)*T;
from the second switching mode to the third switching mode at T/2;
from the third switching mode to the fourth switching mode at D*T; and
from the fourth switching mode to the first switching mode at T, where T is a period and D is the duty cycle.
14. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being less than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the second and third transistors are closed and the first and fourth transistors are open;
a second switching mode in which the first and third transistors are closed and the second and fourth transistors are open;
a third switching mode in which the second, third, and fourth transistors are open and the first transistor is open;
a fourth switching mode in which the first and fourth transistors are closed and the second and third transistors are open;
a fifth switching mode in which the first and third transistors are closed and the second and fourth transistors are open; and
a sixth switching mode in which the first, second, and fourth transistors are open and the third transistor is open.
15. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being less than 50%, the controller is configured to operate sequentially or non-sequentially in a first switching mode, a second switching mode, a third switching mode, a fourth switching mode, a fifth switching mode, and a sixth switching mode, and wherein:
during the first switching mode, current is supplied by at least one of the (N−1) capacitors to a load;
during the second switching mode, current is supplied by the inductor to the load;
during the third switching mode, current is not supplied to the load or the (N−1) capacitors;
during the fourth switching mode, at least one of the (N−1) capacitors is charged; and
during the fifth switching mode, current is supplied by the inductor to the load;
during the sixth switching mode, current is not supplied to the load or the (N−1) capacitors.
16. The system of claim 15 wherein the controller is configured to transition:
from the first switching mode to the second switching mode when current is equal to a predetermined current;
from the second switching mode to the third switching mode when current is zero;
from the third switching mode to the fourth switching mode at T/2;
from the fourth switching mode to the fifth switching mode when current is equal to a predetermined current;
from the fifth switching mode to the sixth switching mode when current is zero; and
from the sixth switching mode to the first switching mode at T, where T is a period.
17. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being greater than 50%, the controller is configured to control states of the first, second, third, and fourth transistors sequentially or non-sequentially in:
a first switching mode in which the first and third transistors are open and the second and fourth transistors are closed;
a second switching mode in which the second and third transistors are closed and the first and fourth transistors are open;
a third switching mode in which the first, third, and fourth transistors are open and the second transistor is closed;
a fourth switching mode in which the first and third transistors are open and the second and fourth transistors are closed;
a fifth switching mode in which the first and fourth transistors are closed and the second and third transistors are open; and
a sixth switching mode in which the first, second, and third transistors are open and the fourth transistor is closed.
18. The system of claim 1 wherein when operating in a discontinuous conduction mode with a ratio of the output voltage of the step-up converter to the input voltage of the step-up converter being greater than 50%, the controller is configured to operate sequentially or non-sequentially in a first switching mode, a second switching mode, a third switching mode, a fourth switching mode, a fifth switching mode, and a sixth switching mode, and wherein:
during the first and fourth switching modes, current flows to ground;
during the second switching mode, current is supplied by at least one of the (N−1) capacitors to a load;
during the fifth switching mode, at least one of the (N−1) capacitors is charged; and
during the third and sixth switching modes, current is not supplied to the load or the (N−1) capacitors.
19. The system of claim 18 wherein the controller is configured to transition:
from the first switching mode to the second switching mode when current is equal to a predetermined current;
from the second switching mode to the third switching mode when current is zero;
from the third switching mode to the fourth switching mode at T/2;
from the fourth switching mode to the fifth switching mode when current is equal to the predetermined current;
from the fifth switching mode to the sixth switching mode when current is zero; and
from the sixth switching mode to the first switching mode at T, where T is a period.
20. A method comprising:
receiving an input voltage at an inductor of a step-up converter, the step-up converter including N transistor pairs connected in series, where N is an integer greater than two, first and second transistors of a first pair of the N transistor pairs being connected to a node that is connected to the inductor, third and fourth transistors of a second pair of the N transistor pairs being respectively connected to the first and second transistors, (N−1) capacitors being connected between the N transistor pairs, and an output capacitor being connected to at least one transistor of the N transistor pairs; and
charging the (N−1) capacitors to voltages that are ratios of an output voltage of the step-up converter, wherein the ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.
21. The method of claim 20 further comprising sequentially:
charging a first one of the (N−1) capacitors to 1/N of the output voltage;
charging a second one of the (N−1) capacitors to 2/N of the output voltage; and
charging an (N−1) th one of the (N−1) capacitors to (N−1)/N of the output voltage.
22. The method of claim 20 further comprising initially charging the (N−1) capacitors to the input voltage before charging the (N−1) capacitors to the voltages that are ratios of the output voltage.
23. The method of claim 20 further comprising charging the (N−1) capacitors to the voltages that are ratios of the output voltage before beginning operation of the step-up converter.
24. The method of claim 20 further comprising charging an (N−1) th one of the (N−1) capacitors to (N−1)/N of the output voltage.
25. The method of claim 20 further comprising:
sensing the voltages across the (N−1) capacitors; and
adjusting duty cycles of the N transistor pairs to maintain the ratios of the voltages.
26. The method of claim 20 further comprising:
sensing current supplied by the inductor; and
transitioning between switching modes of the N transistor pairs based on the current supplied by the inductor.
27. A system comprising:
an inductor including a first terminal in communication with an input voltage supply of a step-up converter;
N transistor pairs connected in series, where N is an integer greater than one, wherein first and second transistors of a first pair of the N transistor pairs are connected to a node, wherein the node is in communication with a second terminal of the inductor, and wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors connected between the N transistor pairs, respectively;
an output capacitor in communication with at least one transistor of the N transistor pairs; and
a controller configured to
generate a first signal when the N transistor pairs are ready to switch;
charge the (N−1) capacitors to the input voltage;
generate a second signal charging the (N−1) capacitors is complete; and
sequentially charge the (N−1) capacitors to (N−1) fractions of an output voltage of the step-up converter in response to the first signal and the second signal.
28. The system of claim 27 wherein the controller is configured to charge an (N−1) th one of the (N−1) capacitors to (N−1)/N of the output voltage.