Dynamic thread sharing in branch prediction structures
Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
1. A computer implemented method for dynamically evaluating how to share, among threads that are being tracked in a processor circuit, entries of a multithreaded branch prediction structure, the method comprising:
receiving a search request to locate branch prediction information associated with said search request;
searching, by said processor circuit, in a first-level branch prediction structure for conditionally matching first-level entries corresponding to the search request;
said first-level entries each including a thread state;
wherein the thread state comprises a first thread state portion having at least one data field that identifies either a share-state or a no-share state of threads that are being tracked in the processor circuit;
wherein the thread state further comprises a second thread state portion having at least one data field that identifies context thread information of threads that are being tracked in the processor circuit;
wherein conditionally matching first-level entries corresponding to the search request comprises satisfying either of a first condition or a second condition;
wherein satisfying said first condition comprises determining that said at least one data field of said first thread state portion identifies said share-state;
wherein satisfying said second condition comprises determining that said second thread state portion matches a portion of the search request;
initially allowing, by said processor circuit, said conditionally matching first-level entries; and
not allowing, by said processor circuit, specific ones of said conditionally matching first-level entries based on determining that said specific ones of said conditionally matching first-level entries previously caused a problem on at least one of threads corresponding to said thread states of said specific ones of said conditionally matching first-level entries.
2. The computer implemented method of claim 1 further comprising, in response to said problem, updating said first thread state portion of said each first-level entries.
3. The computer implemented method of claim 1 wherein said problem comprises a bad branch presence prediction associated with said at least one of the threads.
4. The computer implemented method of claim 1 wherein said first portion of said thread state comprises setting a thread sharing data field.
5. The computer implemented method of claim 1 wherein said at least one data field that identifies context thread information comprises a thread context tag.
6. The computer implemented method of claim 5 wherein:
said determining comprises identifying a conflict mode; and
said conflict mode comprises a mismatch between said thread context tag and said context state information.
7. The computer implemented method of claim 1 wherein:
said branch prediction structure is hierarchical and includes:
a second-level branch prediction structure; and
the processor circuit communicatively coupled to the second-level branch prediction structure, wherein the method of claim 1 further comprises:
based on failing to locate a matching first-level entry in the first-level branch prediction structure corresponding to the search request, initiating, by the processor circuit, a secondary search to locate matching second-level entries in the second-level branch prediction structure;
said second level entries each including a second-level thread state;
initially allowing, by said processor circuit, said conditionally matching second-level entries; and
not allowing, by said processor circuit, specific ones of said conditionally matching second-level entries based on second-level threads state of said second-level specific ones indicating that said second-level specific ones of said conditionally matching second-level entries previously caused a problem on at least one of the threads corresponding to said second-level thread states.