IP Library Granted Patent US 9,899,303
Granted Patent B2
US 9,899,303 · App. 14/862,457 · Granted Feb 20, 2018

Electronic package and fabrication method thereof

Inventors: Yan-Heng Chen (Taichung, TW); Chun-Tang Lin (Taichung, TW); Mu-Hsuan Chan (Taichung, TW); Chieh-Yuan Chi (Taichung, TW)
Assignee: Siliconware Precision Industries Co., Ltd.
H01L23/49811H01L23/5389H01L24/19H01L24/20H01L25/105H01L25/50H01L21/486H01L21/568H01L24/96H01L2224/04105H01L2224/12105H01L2225/1035H01L2225/1041H01L2225/1058H01L2924/18162
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Quick Facts
Patent No.
US 9,899,303
App. No.
14/862,457
Granted
Feb 20, 2018
Kind
B2
Abstract

A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Claims (15)

1. An electronic package, comprising:

an insulating layer having a first surface and a second surface opposite to the first surface, wherein at least a first via hole and a second via hole extending from the first via hole are formed in the insulating layer, the first via hole having a first end communicating with the first surface of the insulating layer and a second end opposite to the first end, the second via hole having a third end communicating with the second surface of the insulating layer and a fourth end opposite to the third end, and the second end of the first via hole communicating with the fourth end of the second via hole, and wherein a width of the first end of the first via hole is greater than a width of the second end of the first via hole, and a width of the third end of the second via hole is greater than a width of the fourth end of the second via hole;

at least an electronic element embedded in the insulating layer;

at least a first conductor correspondingly formed in the first via hole of the insulating layer, wherein a top surface of the first conductor forms a bottom of the second via hole; and

a first circuit structure formed on the first surface of the insulating layer and electrically connected to the electronic element and the first conductor.

2. The package of claim 1 , wherein the electronic element has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface.

3. The package of claim 2 , wherein the first surface of the insulating layer is flush with the active surface of the electronic element.

4. The package of claim 2 , wherein the second surface of the insulating layer is flush with the inactive surface of the electronic element.

5. The package of claim 1 , wherein the first conductor is a metal post or a metal ball.

6. The package of claim 1 , further comprising a second circuit structure formed on the second surface of the insulating layer and electrically connected to the first conductor.

7. The package of claim 6 , wherein the second circuit structure is electrically connected to the electronic element.

8. The package of claim 1 , further comprising at least a second conductor correspondingly formed in the second via hole of the insulating layer.

9. The package of claim 8 , wherein the second conductor is electrically connected to the first conductor.

10. The package of claim 8 , wherein the second conductor is a metal post.

11. The package of claim 1 , further comprising an electronic package structure stacked on the first surface or the second surface of the insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2015
From: CHEN, YAN-HENG; LIN, CHUN-TANG; CHAN, MU-HSUAN; CHI, CHIEH-YUAN
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 036634/0031 →
Priority Claims (1)
TW 103135624 A · Oct 15, 2014 · national
Continuity (1)
Related Publication 20160111359A1 · Apr 21, 2016