Semiconductor device comprising auxiliary trench structures and integrated circuit
An embodiment of a semiconductor device comprises a trench transistor cell array in a semiconductor body. The semiconductor device further comprises an edge termination region of the trench transistor cell array. At least two first auxiliary trench structures extend into the semiconductor body from a first side and are consecutively arranged along a lateral direction. The edge termination region is arranged, along the lateral direction, between the trench transistor cell array and the at least two first auxiliary trench structures. First auxiliary electrodes in the at least two first auxiliary trench structures are electrically connected together and electrically decoupled from electrodes in trenches of the trench transistor cell array.
1. A semiconductor device, comprising:
a trench transistor cell array in a semiconductor body,
an edge termination region of the trench transistor cell array,
at least two first auxiliary trench structures extending into the semiconductor body from a first side and being consecutively arranged along a lateral direction, wherein
the edge termination region is arranged, along the lateral direction, between the trench transistor cell array and the at least two first auxiliary trench structures,
first auxiliary electrodes in the at least two first auxiliary trench structures are electrically connected together and electrically decoupled from electrodes in trenches of the trench transistor cell array, wherein the first auxiliary electrodes are electrically connected to a drain contact of the trench transistor cell array, or to a substrate contact electrically connected to a semiconductor substrate of the semiconductor body, or to a contact at a second side of the semiconductor body opposite to the first side.
2. The semiconductor device of claim 1 , wherein the trenches of the trench transistor cell array are gate electrode trenches, each one of the gate electrode trenches including a gate electrode and a gate dielectric.
3. The semiconductor device of claim 1 , wherein each one of the at least two first auxiliary trench structures includes a single first auxiliary electrode.
4. The semiconductor device of claim 1 , wherein each one of the at least two first auxiliary trench structures includes at least two first auxiliary electrodes.
5. The semiconductor device of claim 1 , wherein an extension of the edge termination region along the lateral direction between the trench transistor cell array and the at least two first auxiliary trench structures ranges between 5 .mu.m and 500 .mu.m.
6. The semiconductor device of claim 5 , further comprising, in the trench transistor cell array, source regions electrically connected to contacts through a surface of the semiconductor body at the first side, wherein the source regions and the contacts connected to the source regions are absent in a semiconductor region between the at least two first auxiliary trench structures.
7. The semiconductor device of claim 5 , further comprising, in the trench transistor cell array, source regions electrically connected to contacts through a surface of the semiconductor body at the first side, wherein the source regions and the contacts connected to the source regions are absent in the edge termination region.
8. The semiconductor device of claim 5 , wherein the edge termination region includes an edge termination trench structure, wherein a thickness of a dielectric in the edge termination trench structure is greater than a thickness of a gate dielectric of a gate trench structure in the trench transistor cell array at a vertical level of a center of a gate electrode in the gate trench structure.
9. The semiconductor device of claim 1 , wherein a pitch between adjacent first auxiliary trench structures along the lateral direction equals a pitch between adjacent gate trench structures in the trench transistor cell array along the lateral direction.
10. The semiconductor device of claim 1 , wherein a geometry of the at least two first auxiliary trench structures projected to a surface area of the semiconductor body at the first side equals a geometry between adjacent gate trench structures in the trench transistor cell array.
11. The semiconductor device of claim 1 , wherein an area of the at least two first auxiliary trench structures projected to a surface area of the semiconductor body at the first side overlaps a contact pad area at the first side.
12. The semiconductor device of claim 1 , wherein the at least two first auxiliary trench structures are arranged, along the lateral direction, between a first trench transistor cell array and a second trench transistor cell array.
13. The semiconductor device of claim 1 , further comprising at least two second auxiliary trench structures extending into the semiconductor body from the first side and being consecutively arranged along the lateral direction, wherein
the at least two first auxiliary trench structures are arranged, along the lateral direction, between the at least two second auxiliary trench structures and the edge termination region; and
second auxiliary electrodes in the at least two second auxiliary trench structures are electrically connected together and electrically decoupled from electrodes in the trenches of the trench transistor cell array and from the first auxiliary electrodes in the at least two first auxiliary trench structures.
14. An integrated circuit, comprising:
a sensor device including a wiring in a sensor trench structure extending into a semiconductor body from a first side;
a first auxiliary trench structure nonadjacent to a source region and different from a gate trench structure of a transistor cell array and extends into the semiconductor body from the first side, the first auxiliary trench structure and the sensor trench structure being arranged directly one after another along a lateral direction, wherein
a first auxiliary electrode in the first auxiliary trench structure is electrically decoupled from the wiring in the sensor trench structure and electrically decoupled from electrodes in trenches of a trench transistor cell array, wherein the first auxiliary electrode is electrically connected to a drain contact of the trench transistor cell array, or to a substrate contact electrically connected to a semiconductor substrate of the semiconductor body, or to a contact at a second side of the semiconductor body opposite to the first side.
15. The integrated circuit of claim 14 , further comprising a second auxiliary trench structure extending into the semiconductor body from the first side, the first auxiliary trench structure, the sensor trench structure and the second auxiliary trench structure being arranged directly one after another along the lateral direction.
16. The integrated circuit of claim 14 , the first auxiliary trench structure, the sensor trench structure and a circuit element are arranged directly one after another along the lateral direction.