IP Library › Granted Patent US 9,900,102
Granted Patent B2
US 9,900,102 · App. 14/956,191 · Granted Feb 20, 2018

Integrated circuit with chip-on-chip and chip-on-substrate configuration

Inventors: Olufemi I. Dosunmu (San Jose, CA); Myung Jin Yim (San Jose, CA); Ansheng Liu (Cupertino, CA)
Assignee: Intel Corporation
H04B10/40H01L25/167H01L25/50
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,900,102
App. No.
14/956,191
Granted
Feb 20, 2018
Kind
B2
Abstract

Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, the apparatus may include an optical transceiver with an opto-electronic component disposed in a first portion of a die, and a trace coupled with the opto-electronic component and disposed to extend to a surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration. The apparatus may include a second trace disposed in the second portion of the die to extend to the surface in the second portion, to provide electrical connection for the other integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration. Other embodiments may be described and/or claimed.

Claims (33)

1. An integrated circuit assembly, comprising:

a first integrated circuit disposed in a first portion of a die proximate to a first surface of the die, wherein the die includes the first portion and a second portion adjacent to the first portion, wherein the first surface of the die extends to the first and second portions of the die, wherein the first integrated circuit comprises an optical transceiver with an opto-electronic component comprising a normal-incidence photodetector (NIPD);

at least a trace coupled with the opto-electronic component and disposed proximate to the first surface of the die to extend substantially to the first surface in the second portion of the die;

a second integrated circuit comprising a receiver, that is disposed in the second portion of the die outside of the first portion of the die, in a chip-on-chip configuration with the first integrated circuit, wherein the trace is to provide electrical connection between the optical transceiver of the first integrated circuit and the second integrated circuit; and

an array of lenses optically coupled with the optical transceiver and disposed on a second surface of the die, opposite the first surface, in the first portion of the die.

2. The integrated circuit assembly of claim 1 , wherein a substrate is to be disposed over at least a third portion of the die in a chip-on-substrate configuration with the second integrated circuit.

3. The integrated circuit assembly of claim 2 , wherein the NIPD is to receive an optical signal and transmit a corresponding electrical output signal via the trace, wherein the second integrated circuit comprises a receiver, to amplify the electrical output signal and to provide the amplified electrical output signal to circuitry disposed in the substrate via at least a second trace.

4. The integrated circuit of claim 3 , wherein the trace is a first trace, wherein the first trace comprises a first plurality of traces, to electrically couple the NIPD with inputs of the receiver.

5. The integrated circuit assembly of claim 4 , further comprising at least a second trace that includes a second plurality of traces, to electrically couple outputs of the receiver with the circuitry disposed in the substrate.

6. The integrated circuit assembly of claim 5 , wherein at least one of the second plurality of traces comprises a reflector, to provide a determined optical response for the NIPD.

7. The integrated circuit assembly of claim 5 , wherein the second plurality of traces are disposed in the second portion of the die in a multi-layered fashion.

8. The integrated circuit assembly of claim 5 , wherein the first and second plurality of traces include contact pads disposed at respective ends of traces to extend to the first surface of the die, to provide electrical connectivity for the first and second integrated circuits and the circuitry disposed in the substrate.

9. The integrated circuit assembly of claim 4 , wherein each of the lenses includes a facet, to prevent formation of resonant cavities between the lenses and the NIPD.

10. The integrated circuit assembly of claim 9 , wherein the die includes a distributed Bragg reflector multilayer stack, to provide a determined optical response for the NIPD.

11. The integrated circuit assembly of claim 1 , wherein the assembly comprises a printed circuit board (PCB).

12. An apparatus comprising:

a processor;

a first integrated circuit comprising an optical transceiver communicatively coupled with the processor, and including an opto-electronic component-disposed in a first portion of a die, proximate to a first surface of the die, wherein the opto-electronic component comprises a normal-incidence photodetector (NIPD);

a second integrated circuit comprising a receiver, that is disposed in a second portion of the die outside of the first portion of the die, in a chip-on-chip configuration with the first integrated circuit;

at least a trace coupled with the opto-electronic component and disposed proximate to the first surface of the die to extend substantially to the first surface in the second portion of the die adjacent to the first portion, to provide electrical connection for the optical transceiver and the second integrated circuit; and

an array of lenses optically coupled with the optical transceiver and disposed on a second surface of the die, opposite the first surface, in the first portion of the die.

13. The apparatus of claim 12 , further comprising a substrate disposed over at least the second portion of the die in a chip-on-substrate configuration with the second integrated circuit.

14. The apparatus of claim 13 , wherein the substrate comprises a printed circuit board (PCB), wherein the apparatus comprises a mobile computing device.

15. A method, comprising:

providing a first integrated circuit, including disposing an opto-electronic component of an optical transceiver in a first portion of a die, proximate to a first surface of the die, wherein the die includes a first portion and a second portion adjacent to the first portion, wherein the first surface of the die extends to the first and second portions of the die, the opto-electronic component comprising a normal-incidence photodetector (NIPD);

disposing at least a trace proximate to the first surface of the die, including extending the at least a trace substantially to the first surface in the second portion of the die adjacent to the first portion;

providing a second integrated circuit comprising a receiver, including disposing the receiver in the second portion of the die outside of the first portion of the die, on the first surface;

coupling the opto-electronic component with the at least a trace, to provide electrical connection for the optical transceiver and the second integrated circuit in a chip-on-chip configuration;

and

disposing an array of lenses on a second surface of the die, opposite the first surface, in the first portion of the die, to be optically coupled with the optical transceiver.

16. The method of claim 15 , wherein disposing the array of lenses on the die includes providing the array of lenses above the first portion of the die.

17. The method of claim 15 , further comprising:

disposing a substrate over at least the second portion of the die in a chip-on-substrate configuration.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2015
From: DOSUNMU, OLUFEMI I.; YIM, MYUNG JIN; LIU, ANSHENG
To: INTEL CORPORATION
Reel/Frame 037182/0982 →
Continuity (1)
Related Publication 20170155450A1 · Jun 1, 2017