Display panel having daisy-chain-connected pixels, pixel chip, and electronic apparatus

1. A display panel, comprising:

a plurality of first unit pixels, each of the plurality of first unit pixels including:

a first data input terminal;

a first data output terminal;

a display element, wherein the display element is configured to display based on first data and second data,

wherein the first data is inputted to the first data input terminal, and

wherein the first data comprises a header portion and a ddata portion;

a first waveform shaping section,

wherein the first waveform shaping section is on a first signal path from the first data input terminal to the first data output terminal;

a second data input terminal;

a second data output terminal; and

a second waveform shaping section on a second signal path from the second data input terminal to the second data output terminal,

wherein the second data includes a data portion to discriminate, for each first unit pixel, intensity data in the first data, and

wherein the second data is inputted to the second data input terminal.

2. The display panel according to claim 1 ,

wherein the first waveform shaping section is a flip-flop.

3. The display panel according to claim 1 ,

wherein the first waveform shaping section is a buffer.

4. The display panel according to claim 1 ,

wherein each of the plurality of first unit pixels further includes a plurality of display elements, and

wherein the plurality of display elements are configured to display in different colors.

5. The display panel according to claim 1 ,

wherein the display element is an LED display element.

6. The display panel according to claim 1 , further comprising a drive section,

wherein the first data input terminal of a first unit pixel of the plurality of first unit pixels is connected to the first data output terminal of a second unit pixel of the plurality of first unit pixels, and

wherein the drive section is configured to supply the first data to a first-stage first unit pixel of the plurality of first unit pixels.

7. The display panel according to claim 6 , further comprising a plurality of second unit pixels,

wherein a first unit pixel of the plurality of second unit pixels is connected to the first data output terminal in the first unit pixel of the plurality of first unit pixels.

8. The display panel according to claim 1 ,

wherein each of the plurality of first unit pixels further includes:

a first clock input terminal;

a first clock output terminal; and

a first buffer,

wherein the first buffer is provided on a first clock signal path from the first clock input terminal to the first clock output terminal.

9. The display panel according to claim 8 ,

wherein each of the plurality of first unit pixels further includes:

a second clock input terminal;

a second clock output terminal; and

a second buffer,

wherein the second buffer is provided on a second clock signal path from the second clock input terminal to the second clock output terminal, and

wherein a first signal level of a first clock is an inverse of a second signal level of a second clock,

wherein the first clock is inputted to the first clock input terminal, and

wherein the second clock is inputted to the second clock input terminal.

10. The display panel according to claim 9 ,

wherein a latch circuit is between the first clock signal path and the second clock signal path.

11. The display panel according to claim 1 ,

wherein each of the plurality of first unit pixels further includes:

a first clock input terminal;

a second clock input terminal;

a first clock output terminal to be connected to the first clock input terminal in a subsequent-stage first unit pixel;

a second clock output terminal to be connected to the second clock input terminal in the subsequent-stage first unit pixel;

a first inverter on a first clock signal path from the first clock input terminal to the second clock output terminal; and

a second inverter on a second clock signal path from the second clock input terminal to the first clock output terminal.

12. The display panel according to claim 11 , wherein a first length of the first clock signal path is different from a second length of the second clock signal path.

13. The display panel according to claim 1 ,

wherein the ddata portion includes intensity data that defines emission intensity in the display element, and

wherein each of the plurality of first unit pixels further includes a memory section,

wherein the memory section is configured to store the intensity data, and

wherein the display element is further configured to display based on the stored intensity data.

14. The display panel according to claim 13 ,

wherein each of the plurality of first unit pixels further includes a converting section that is configured to execute digital-to-analog (D/A) conversion of the stored intensity data, and

wherein the display element is further configured to display based on the D/A-converted intensity data.

15. The display panel according to claim 13 ,

wherein the ddata portion further includes a flag,

wherein the ddata portion is inputted to a first unit pixel of the plurality of first unit pixels,

wherein the flag indicates that the intensity data has been read in a second unit pixel arranged anteriorly to the first unit pixel, and

wherein each of the plurality of first unit pixels is configured to distinguish, based on the flag, the intensity data of a relevant first unit pixel from the intensity data of the plurality of first unit pixels included in the ddata portion.

16. The display panel according to claim 13 ,

wherein each of the plurality of first unit pixels is associated with an address, and

wherein each of the plurality of first unit pixels is configured to distinguish, based on the address, the intensity data of a relevant first unit pixel from the intensity data of the plurality of first unit pixels included in the ddata portion.

17. The display panel according to claim 13 ,

wherein each of the plurality of first unit pixels further includes a pulse generating section that is configured to generate a pulse signal having a pulse width based on the stored intensity data, and

wherein the display element is further configured to display based on the generated pulse signal.

18. The display panel according to claim 17 ,

wherein the pulse generating section is configured with a counter.

19. The display panel according to claim 17 ,

wherein the first waveform shaping section, the memory section, and the pulse generating section constitute a chip for each first unit pixel.

20. An electronic apparatus, comprising:

a display panel; and

a control section configured to control display on the display panel,

wherein the display panel includes:

a plurality of first unit pixels, each of the plurality of first unit pixels including:

a first data input terminal;

a first data output terminal;

a display element, wherein the display element is configured to display based on first data and second data,

wherein the first data is inputted to the first data input terminal, and

wherein the first data comprises a header portion and a ddata portion;

a first waveform shaping section,

wherein the first waveform shaping section is on a first signal path from the first data input terminal to the first data output terminal;

a second data input terminal;

a second data output terminal; and

a second waveform shaping section on a second signal path from the second data input terminal to the second data output terminal,

wherein the second data includes a data portion to discriminate, for each first unit pixel, intensity data in the first data, and

wherein the second data is inputted to the second data input terminal.