Structure for die probing
A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A molding material encircles the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die, with a bottom surface of the dielectric layer contacting a top surface of the device die and a top surface of the molding material. A redistribution line (RDL) extends into the dielectric layer to electrically couple to the metal pillar.
1. A method comprising:
forming solder regions on top surfaces and sidewalls of metal pillars of a device die;
probing the device die by contacting probe pins to the solder regions;
after the probing, encapsulating the device die in an encapsulating material;
planarizing the device die and the encapsulating material, wherein at least portions of the solder regions over the metal pillars are removed;
forming a dielectric layer over and contacting the device die and the encapsulating material; and
forming redistribution lines comprising via portions penetrating through the dielectric layer, wherein each of the via portions is in contact with at least one of the solder regions and the metal pillars.
2. The method of claim 1 , wherein all portions of the solder regions over top surfaces of the metal pillars are removed by the planarizing, and the via portions of the redistribution lines are in physical contact with the top surfaces of the metal pillars.
3. The method of claim 1 , wherein after the planarizing, portions of the solder regions are left overlapping the metal pillars, and the via portions of the redistribution lines are in physical contact with top surfaces of the portions of the solder regions.
4. The method of claim 1 further comprising:
encapsulating a through-via in the encapsulating material, wherein after the planarizing, a top surface of the through-via is level with a top surface of the encapsulating material, wherein one of the redistribution lines comprises an additional via portion penetrating through the dielectric layer, and the additional via portion is in contact with the top surface of the through-via.
5. The method of claim 1 further comprising applying a polymer layer to cover the solder regions, wherein after the planarization, a top surface of the polymer layer is coplanar with a top surface of the encapsulating material.
6. The method of claim 1 further comprising, after the probing, performing a die saw to separate the device die from other device dies of a respective wafer.
7. The method of claim 1 , wherein the forming the solder regions comprises:
plating the solder regions; and
reflowing the solder regions.
8. A method comprising:
forming a solder region on a top surface of a metal pillar in a device die;
probing the device die by contacting a probe pin to the solder region; and
after the probing, removing at least a top portion of the solder region to generate a top surface, wherein the top surface comprises at least one or both of a top surface of the solder region and a top surface of the metal pillar.
9. The method of claim 8 , wherein in the removing, all of the solder region over the top surface of the metal pillar is removed.
10. The method of claim 9 , wherein after the removing, a portion of the solder region on a sidewall of the metal pillar remains.
11. The method of claim 10 , wherein the portion of the solder region remaining on the sidewall of the metal pillar contacts an upper portion of the sidewall of the metal pillar, and a bottom end of the portion of the solder region is higher than a lower portion of the sidewall of the metal pillar.
12. The method of claim 8 further comprising:
encapsulating the device die in a molding compound; and
planarizing the molding compound to expose at least one of the metal pillar and the solder region, wherein the removing is achieved by the planarizing.
13. The method of claim 12 further comprising:
forming a dielectric layer over and contacting the device die and the molding compound; and
forming a redistribution line comprising a via portion penetrating through the dielectric layer, wherein the via portion is electrically coupled to the metal pillar.
14. The method of claim 8 , wherein after the removing, a portion of the solder region remains to cover the metal pillar.
15. A method comprising:
plating a solder region on a top surface of a metal pillar of a device die;
reflowing the solder region;
encapsulating the device die in an encapsulating material;
planarizing the device die and the encapsulating material to reveal the metal pillar; and
forming a dielectric layer over and contacting the device die and the metal pillar.
16. The method of claim 15 , wherein when the solder region is plated, the device die is a portion of an un-sawed wafer, and the method further comprising:
after the solder region is reflowed, probing on the solder region; and
sawing the un-sawed wafer into a plurality of device dies comprising the device die.
17. The method of claim 16 further comprising, before sawing the un-sawed wafer and after the probing, applying a polymer layer on the un-sawed wafer to cover the solder region.
18. The method of claim 15 , wherein after the device die is planarized, a portion of the solder region remains.
19. The method of claim 18 , wherein the remaining portion of the solder region comprises a portion directly over the metal pillar.
20. The method of claim 18 , wherein the remaining portion of the solder region comprises a portion on a sidewall of the metal pillar.